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stc technology co.,ltd. stc12c5a08/16/32/60 8-bit micro-controller this document contains information on a new product under devel opment by stc.stc reserves the right to change or discontinue th is product without notice. 2007/12 version a1 features ...................................................................................................................... ....... 3 ? general description .......................................................................................................... 4 ? order information: ............................................................................................................ 4 ? pin description ............................................................................................................... ... 5 ? pin definition ............................................................................................................ 5 ? pin configuration ...................................................................................................... 7 ? block diagram ................................................................................................................. . 9 ? address map ........................................................................................................... 10 ? bits description ...................................................................................................... 11 ? memory ........................................................................................................................ ... 13 ? organization ............................................................................................................ 13 ? ram ....................................................................................................................... 13 ? embedded flash ...................................................................................................... 14 ? ale output ................................................................................................................ 15 ? functional description .................................................................................................... 17 ? i/o port configuration ............................................................................................ 17 ? timer/counter ......................................................................................................... 21 ? baud-rate generator(brt) ....................................................................... 25 ? interrupt ................................................................................................................... 2 7 ? watch dog timer .................................................................................................... 34 ? universal asynchronous serial port (uart) ......................................................... 36 ? secondary universal asynchronous serial port (s2) ............................................. 40 ? programmable counter array (pca) ...................................................................... 45 ? serial peripheral interface(spi) .............................................................................. 55 ? analog to digital converter .................................................................................... 63 ? power management ................................................................................................ 66 ? in system programming and in application programming .................................... 69 ? in system programming (isp) ................................................................................ 69 ? in-application program (iap) ................................................................................ 72 ? instructions set .............................................................................................................. .. 72 ? absolute maximum rating (stc12c5axx) .................................................................. 75 ? dc characteristics (stc12c5axx) ................................................................................ 75 ? absolute maximum rating (stc12le5axx) ................................................................ 76 ? dc characteristics (stc12le5axx) ............................................................................. 76 ? package dimension ......................................................................................................... 77 ? http://www..net/ datasheet pdf - http://www..net/
2 stc12c5axx technical summary version history ............................................................................................................... 78 ? http://www..net/ datasheet pdf - http://www..net/
stc12c5axx technical summary 3 features z enhanced 80c51 central processing unit z 3.3v/5v operation voltage, built-in lo w-voltage detector and reset circuit z operation frequency range up to 25mhz z max 64k bytes on-chip flash memory with isp/iap capability z 256 byte scratch-pad ram and 1024 bytes of auxiliary ram z two-level code protection for flash memory access z two 16-bit timer/counter z 10 sources, 4-level-prio rity interrupt capability z secondary uart2 with self baud-rate generator z one enhanced uart with automatic address recognition and frame error detection z spi master/slave communication interface z 15 bits watch-dog-timer with 8-bit pre-scalar, one-time enabled z two channel programmable counter array (pca) z 10-bit analog-to-digital converter (adc) z power control: idle mode and power-down mode, power-down can be woken-up through int0 and int1 z 44(max) programmable i/o ports z alternative built-in 6mhz oscillator z fully static operation z excellent noise immunity z very low power consumption z package type: -pdip-40: -lqfp-44 -pqfp-44 -plcc-44 http://www..net/ datasheet pdf - http://www..net/
4 stc12c5axx technical summary general description stc12c5axx is a single-chip 8-bit micro-controller with instruction sets fully compatible with industrial-standard 80c51 series micro controller. there is very excellent mcu kernel built in this device compared to general 80c51 mcus those take twelve oscillating cycles to finish an instruction, the device could take only one oscillating cycle to finish one instruction. there is 8k(max) bytes flash memory embedded which could be used as program or data. also the in-system programming and in -application programming mechanisms are supported. the data endurance of the embedded flash gets over 20,000 times, and 21 years data retention is guaranteed. the operation frequency reaches at 25mhz. an user can apply a crystal oscillator for the oscillating source, or alternativel y uses the built in 6mhz rc osci llator to save system cost. the built in 10bits analog-to-digital converter make it easy to sensing the environment or implement a set of scan keys in low cost. the uart interfaces make the device conv enient to communicate with the peripheral component, say talking to a personal computer via rs-232 port, or communicating with a serial memory. the pulse-width-modulator (pwm) and programma ble counter array (pca) make the device to drive the peripheral step motor or led in least cost. the stc12xx is really the most efficient mc u adapted for simple control, say electronic scales, remote controller, security encoder/ decoder, and user interface controller. order information: part number temperature range package packing operation voltage 12x5aaa-bbb-cc-d-eee-ff -40 ~+85 pdip-40 tray le3.3v/ c:5v 12x5aaa-bbb-cc-d-eee-ff -40 ~+85 plcc-44 tray le3.3v/ c:5v 12x5aaa-bbb-cc-d-eee-ff -40 ~+85 lqfp-48 tray le3.3v/ c:5v 12x5aaa-bbb-cc-d-eee-ff -40 ~+85 lqfp-44 tray le3.3v/ c:5v .x: voltage aa: rom size bbb:adc,p wm .or. none cc:active frequency .d: temperature ?i? for industrial eeee: package type ff: pin count http://www..net/ datasheet pdf - http://www..net/
stc12c5axx technical summary 5 pin description pin definition mnemonic package type description pdip40 plcc44 pqfp44 lqfp48 p0.0 ~ p0.7 32-39 43-34 37-30 40-33 port0 : port0 is an open-drain, bi-directional io port. when 1s are written to port0, they become high-impedance inputs. port0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. p1.0 /adc0/ clkout2 p1.1/adc1 p1.2/adc2/eci/ rxd2 p1.3/adc3/ccpo/ txd2 p1.4/adc4/ccp1/ss p1.5/adc5/mosi p1.6/adc6/miso p1.7/adc7/sclk 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 40 41 42 43 44 1 2 3 43 44 45 46 47 2 3 4 port1 : general-purposed i/o with weak pull-up resistance inside. when 1s are written into port1, the strong output driving pmos only turn-on two period and then the weak pull-up resistance keep the port high. adcn : analog to digital converter input. p2.0 ~ p2.7 21-28 24-31 18-25 19-23 26-28 port2 : port2 is an 8-bit bi-directional i/o port with pull-up resistance. except being as gpio, port2 emits the high-order address byte during accessing to external program and data memory. p3.0/rxd p3.1/txd p3.2/int0 p3.3/int1 p3.4/t0/clkout0 p3.5/t1/clkout1 p3.6/wr p3.7/rd 10-17 11 13 14 15 16 17 18 19 5 7 8 9 10 11 12 13 6 8 9 10 11 12 13 14 port3 : general-purposed i/o with weak pull-up resistance inside. when 1s are written into port1, the strong output driving pmos only turn-on two period and then the weak pull-up resistance keep the port high. port3 also serves the special function of stc12c5axx. http://www..net/ datasheet pdf - http://www..net/
6 stc12c5axx technical summary p4.0/ss p4.1/eci/mosi p4.2/ccp0/miso p4.3/ccp1/sclk p4.4/na p4.5/ale p4.6/ex_lvd/rst2 p4.7/rst 29 30 31 9 23 34 1 12 32 33 35 10 17 28 39 6 26 27 29 4 18 31 42 7 29 30 32 5 port4 : port4 are extended i/o ports such like port1. it can be available only on 44l-plcc, 44l-pqfp and 48l-lqfp. ale : address latch ex_lvd : external low voltage reset detector. reset 9 10 4 5 reset : a high on this pin for at least two machine cycles will reset the device. p5.0 p5.1 p5.2 p5.3 24 25 48 1 port5 : port4 are extended i/o ports such like port1. it can be available only on 48l-lqfp. xtal1 19 21 15 16 crystal1 : input to the inverting oscillator amplifier. xtal2 18 20 14 15 crystal2 : output from the inverting amplifier. vdd 40 44 38 41 power vss 20 22 16 17 ground http://www..net/ datasheet pdf - http://www..net/
stc12c5axx technical summary 7 pin configuration clkout2/p1.0 eci/p1.2 ccp0/p1.3 ss/ccp1/p1.4 mosi/p1.5 miso/p1.6 sclk/p1.7 rst/p4.7 rxd/p3.0 txd/p3.1 int0/p3.2 int1/p3.3 clkout0/t0/p3.4 clkout1/t1/p3.5 wr/p3.6 rd/p3.7 p0.2/ad2 p0.3/ad3 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ex_lvd/p4.6/rst2 ale/p4.5 na/p4.4 p2.7/a15 p2.6/a14 p2.5/a13 p2.4/a12 p2.3/a11 p2.2/a10 p2.1/a9 p2.0/a8 xtal2 xtal1 gnd p0.1/ad1 p0.0/ad0 vdd 1 20 21 40 pdip-40 p1.1 stc12c5axx mosi/p1.5 miso/p1.6 sclk/p1.7 rxd/p3.0 rst/p4.7 txd/p3.1 int0/p3.2 int1/p3.3 clkout0/t0/p3.4 clkout1/t1/p3.5 p3.6/wr p3.7/rd xtal2 xtal1 gnd p4.0/ss p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 p0.4/ad4 p2.5/a13 ss/ccp1/p1.4 ccp0/p1.3 eci/p1.2 clkout2/p1.0 miso/ccp0/p4.2 vdd ad0/p0.0 ad1/p0.1 ad2/p0.2 ad3/p0.3 1 sclk/ccp1/p4.3 stc12c5axx lqfp-48 p0.5/ad5 p0.6/ad6 p4.6/e_lvd/rst2 p0.7/ad7 p4.5/ale na/p4.4 p2.7/a15 p2.6/a14 p4.1/eci/mosi p5.0 p5.1 p5.3 p1.1 p5.2 http://www..net/ datasheet pdf - http://www..net/
stc technology co.,ltd. stc12c5a08/16/32/60 8-bit micro-controller this document contains information on a new product under devel opment by stc.stc reserves the right to change or discontinue th is product without notice. 2007/12 version a1 mosi.p1.5 miso/p1.6 sclk/p1.7 rxd/p3.0 rst/p4.7 txd/p3.1 int0/p3.2 int1/p3.3 clkout0/t0/p3.4 clkout1/t1/p3.5 p3.6/wr p3.7/rd xtal2 xtal1 gnd p4.0/ss p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 p0.4/ad4 p0.5/ad5 p0.6/ad6 ex_lvd/p4.6/rst2 p0.7/ad7 p4.5/ale na/p4.4 p2.7/a15 p2.6/a14 p2.5/a13 ss/ccp1/p1.4 ccp0/p1.3 eci/p1.2 p1.1 clkout2/p1.0 miso/ccp0/p4.2 vdd ad0/p0.0 ad1/p0.1 ad2/p0.2 ad3/p0.3 1 7 40 sclk/ccp1/p4.3 p4.1/eci/mosi 18 29 stc12c5axx plcc-44 mosi/p1.5 miso/p1.6 sclk/p1.7 rxd/p3.0 rst/p4.7 txd/p3.1 int0/p3.2 int1/p3.3 clkout0/t0/p3.4 clkout1/t1/p3.5 p3.6/wr p3.7/rd xtal2 xtal1 gnd p4.0/ss p.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 p0.4/ad4 p2.5/a13 ss/ccp1/p1.4 ccp0/p1.3 eci/p1.2 clkout2/p1.0 miso/ccp0/p4.2 vdd ad0/p0.0 ad1/p0.1 ad2/p0.2 ad3/p0.3 1 sclk/ccp1/p4.3 stc12c5axx pqfp/lqfp-44 p0.5/ad5 p0.6/ad6 p4.6/ex_lvd/rst2 p0.7/ad7 p4.5/ale p4.4/na p2.7/a15 p2.6/a14 p4.1/eci/mosi p1.1 http://www..net/ datasheet pdf - http://www..net/
stc12c5axx technical summary 9 block diagram alu http://www..net/ datasheet pdf - http://www..net/
10 stc12c5axx technical summary special function register address map 9 a b c d e f f8 ch ccap0h ccap1h f0 b pcapwm0 * pcapwm1 * e8 cl ccap0l ccap1l e0 acc d8 ccon cmod ccapm0 ccapm1 d0 psw c8 p5 p5m1 p5m0 spstat spctl spdat c0 p4 wdt_contr iap_data iap_addrh iap_addrl iap_cmd iap_trig iap_contr b8 ip saden p4sw adc_contr adc_res adc_resl b0 p3 p3m1 p3m0 p4m1 p4m0 ip2 ip2h iphiph a8 ie saddr a0 p2 bus_speed auxr1 test_wdt 98 scon sbuf s2con s2sbuf brt p1asf 90 p1 p1m1 p1m0 p0m1 p0m0 p2m1 p2m0 clk_div 88 tcon tmod tl0 tl1 th0 th1 auxr wake_clk0 80 p0 sp dpl dph pcon * write only http://www..net/ datasheet pdf - http://www..net/
stc12c5axx technical summary 11 bits description symbol address map bit address and symbol msb lsb initial value p0 80h xxxx1111b sp 81h 00000111b dpl 82h 00000000b dph 83h 00000000b pcon 87h -- -- -- -- -- -- pd idl xxxxxx00b tcon 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00000000b tmod 89h gate c/t m1 m0 gate c/t m1 m0 00000000b tl0 8ah 00000000b tl1 8bh 00000000b th0 8ch 00000000b th1 8dh 00000000b auxr 8eh t0x12 t1x12 uart_ brtr s2smod brtx12 extram s1brs 00xxxxxxb wake_clko 8fh pca rxd_pin_ t1_pin_ t0_pin_ lvd_wa brtclk t1clko t0clko 00000x00b p1 90h p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 11111111b p1m1 91h p1.7m1 p1.6m1 p1.5m1 p1.4m1 p1.3m1 p1.2m1 p1.1m1 p1.0m1 00000000b p1m0 92h p1.7m0 p1.6m0 p1.5m0 p1.4m0 p1.3m0 p1.2m0 p1.1m0 p1.0m0 00000000b p0m1 93h p0.7m1 p0.6m1 p0.5m1 p0.4m1 p0.3m1 p0.2m1 p0.1m1 p0.0m1 00000000b p0m0 94h p0.7m0 p0.6m0 p0.5m0 p0.4m0 p0.3m0 p0.2m0 p0.1m0 p0.0m0 00000000b p2m1 95h p2.7m1 p2.6m1 p2.5m1 p2.4m1 p2.3m1 p2.2m1 p2.1m1 p2.0m1 00000000b p2m0 96h p2.7m0 p2.6m0 p2.5m0 p2.4m0 p2.3m0 p2.2m0 p2.1m0 p2.0m0 00000000b clk_div 97h clks2 clks1 clks0 xxxxx000b scon 98h sm0 sm1 sm2 ren txsts tisel ti ri 00000000b sbuf 99h sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 xxxxxxxxb s2con 9ah s2sm0 s2sm1 s2sm2 s2ren s2tb8 s2rb8 s2ti s2ri 00000000b s2sbuf 9bh s2d7 s2d6 s2d5 s2d4 s2d3 s2d2 s2d1 s2d0 xxxxxxxxb brt 9ch 00000000b p1sf 9dh p1.7asf p1.6asf p1.5asf p1.4asf p1.3asf p1.2asf p1.1asf p1.0asf 00000000b p2 a0h p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 11111111b bus_speed a1h ales1 ales0 rws2 rws1 rws0 xx100x11b auxr1 a2h pca_p4 spi_p4 s2_p4 gf2 adrj dps 00000000b test_wdt a7h 0xx00000b ie a8h ea -- espi es et1 ex1 et0 ex0 0x000000b saddr a9h -- -- -- -- -- 00000000b ie2 afh espi es2 xxxxxx00b p3 b0h p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 11111111b p3m1 b1h p3.7m1 p3.6m1 p3.5m1 p3.4m1 p3.3m1 p3.2m1 p3.1m1 p3.0m1 00000000b p3m0 b2h p3.7m0 p3.6m0 p3.5m0 p3.4m0 p3.3m0 p3.2m0 p3.1m0 p3.0m0 00000000b p4m1 b3h p4.7m1 p4.6m1 p4.5m1 p4.4m1 p4.3m1 p4.2m1 p4.1m1 p4.0m1 00000000b p4m0 b4h p4.7m0 p4.6m0 p4.5m0 p4.4m0 p4.3m0 p4.2m0 p4.1m0 p4.0m0 00000000b ip2 b5h psp1 ps2 xxxxxx00b ip2h b6h psp1h ps2h xxxxxx00b iph b7h ppcah plvdh padch psh pt1h px1h pt0h px0h 00000000b ip b8h ppca plvd padc ps pt1 px1 pt0 px0 00000000b http://www..net/ datasheet pdf - http://www..net/
12 stc12c5axx technical summary saden b9h 00000000b p4sw bbh lvd_p4.6 ale_p4.5 na/p4.4 x000xxxxb adc_contr bch adc speed1 speed0 adc_ adc_ chs2 chs1 chs0 00000000b adc_res bdh 00000000b adc_resl beh 00000000b p4 c0h 11111111b wdt_contr c1h wdt_ -- en_wdt clr_ idl_ ps2 ps1 ps0 xx000000b iap_data c2h 11111111b iap_address c3h 00000000b iap address c4h 00000000b iap cmd c5h ms1 ms0 xxxxxx00b iap_trig c6h xxxxxxxxb iap_contr c7h iapen swbs swrst cmd_fail wt2 wt1 wt0 00001000b p5 c8h p5m1 c9h p5.7m1 p5.6m1 p5.5m1 p5.4m1 p5.3m1 p5.2m1 p5.1m1 p5.0m1 xxxx0000b p5m0 cah p5.7m0 p5.6m0 p5.5m0 p5.4m0 p5.3m0 p5.2m0 p5.1m0 p5.0m0 xxxx0000b spstat cdh spif wcol 00xxxxxxb spctl ceh ssig spen dord mstr cpol cpha spr1 spr0 00000100b spdat cfh 0000000b psw d0h cy ac f0 rs1 rs0 ov -- p 00000000b ccon d8h cf cr ccf1 ccf0 00xxxx00b cmod d9h cidl cps2 cps1 cps0 ecf 0xxx0000b ccapm0 dah ecomo capp0 capn0 mat0 tog0 pwm0 eccf0 x0000000b ccapm1 dbh ecom1 capp1 capn1 mat1 tog1 pwm1 eccf1 x0000000b acc e0h 00000000b cl e9h wrf -- enw clw widl ps2 ps1 ps0 0x000000b ccap0l eah 11111111b ccap1l ebh 00000000b b f0h 00000000b pca_pwm0 f2h -- -- -- -- -- -- epc0h epc0l xxxxxx00b pca_pwm1 f3h epc1h epc1l xxxxxx00b ch f9h 00000000b ccap0h fah 00000000b ccap1h fbh 00000000b http://www..net/ datasheet pdf - http://www..net/
stc technology co.,ltd. stc12c5a08/16/32/60 8-bit micro-controller this document contains information on a new product under devel opment by stc.stc reserves the right to change or discontinue th is product without notice. 2007/12 version a1 memory organization ram there are 1280 bytes ram built in stc12c5axx. the user can visit the leading 128-byte ram via dire ct addressing instructions, we name those ram as direct ram that occupies address space 00h to 7fh. followed 128-byte ram can be visited via indirect addressing instructions, we name those ram as indirect ram that occupied address space 80h to ff h. there are extra 1024 bytes ram can be visited via movx @ri or @dptr instructions which are named external or auxiliary ram. none of p0 status and p2 status will be affected during movx instruction. a control bit extram located in sfr auxr . 1 register is to control acce ss of auxiliary ram. when set, disable the access of auxiliary ram. when clear (ext ram=0), this auxiliary ram is the default target for the address range from 0x0000 to 0x03ff. if ex tram=0 and the target address is over 0x03ff, stc12c5axx switches to access external ram autom atically. when extram=0, the content in dph is ignored when the instructi on movx @ri is executed. 00-7f ram, access it via direct addressing 80-ff sfr, access it via direct addressing 80-ff indirect on-chip ram, access it via indirect addressing 00 80 ff address space for stc12c5axx ram 7f 0000-03ff on-chip external auxiliary ram. http://www..net/ datasheet pdf - http://www..net/
14 stc12c5axx technical summary embedded flash there is totally 64k byte flash embedded in the stc12c5axx. the user can configure the whole flash to store his application program, or he can configure the flash for both storage of application (ap) program and in-system-program (isp) code, even he can configure the flash for storage of ap, isp, and in-application-program (iap) memory. if there is requirement from the user?s applic ation program to store nonvolatile parameters, the user can allocate part of the embedded flash as iap memory by part no.. http://www..net/ datasheet pdf - http://www..net/
stc technology co.,ltd. stc12c5a08/16/32/60 8-bit micro-controller this document contains information on a new product under devel opment by stc.stc reserves the right to change or discontinue th is product without notice. 2007/12 version a1 ale output as we have known, an 8051 mcu always output s ale the signal. however, the device doesn?t output the ale signal except when accessing the external data memory. access timing stretching for low-speed memory to access the low-speed external data memory , the timing-stretch mechanism is designed to control the access timing of the ?movx? instructions. the bits ales1 and ales0, in bus_speed register, control the stretching of the setup time and hold time with respect to ale negative edge. and, the bits rws2, rws1 and rws0 control the stretching of the read/write pulse width. users should config ure stretch register properly to conform to the read/write requirements of the external data memory being used. bus_speed (address=a1h, external access stretch register) bus_speed register read/write address: 0xa1h default: xx10-x011 bit 7 6 5 4 3 2 1 0 name ales1 ales0 rws2 rws1 rws0 note:the reset value for bus_speed is 00100011b (0x23). that is, {ales1,ales0}={1,0} and {rws2,rws1,rws0}={0,1,1}. {ales1, ales0}: 00: no stretch, the p0?s address setup/hold time to the following ale falling edge is 1 clock cycle. 01: 1 clock stretched, the p0?s address setup/hold time to the following ale falling edge is 2 clock cycles. 10: 2 clocks stretched, the p0?s address setup/ho ld time to the following ale falling edge is 3 clock cycles. 11: 3 clocks stretched, the p0?s address setup/ho ld time to the following ale falling edge is 4 clock cycles. {rws2, rws1, rws0}: 000: no stretch, the movx re ad/write pulse is 1 clock cycle. 001: 1 clock stretched, the movx read/write pulse is 2 clock cycles. 010: 2 clocks stretched, the movx read/write pulse is 3 clock cycles. http://www..net/ datasheet pdf - http://www..net/
16 stc12c5axx technical summary 011: 3 clocks stretched, the movx read/write pulse is 4 clock cycles. 100: 4 clocks stretched, the movx read/write pulse is 5 clock cycles. 101: 5 clocks stretched, the movx read/write pulse is 6 clock cycles. 110: 6 clocks stretched, the movx read/write pulse is 7 clock cycles. 111: 7 clocks stretched, the movx read/write pulse is 8 clock cycles. http://www..net/ datasheet pdf - http://www..net/
stc12c5axx technical summary 17 functional description i/o port configuration there are 44(max) port pins on stc12c5axx may be independently configured to one of four modes: quasi-bidirectional(standard 8051 port output), push-pull output, open-drain output or input-only. all port pins default to quasi-bidi rectional after reset. each port pin has a schmitt-triggered input for improved input noise rejection. during power-down, all the schmitt-triggered inputs are disabled with the exception o f p3.2 (int0) and p3.3 (int1) or rxd_pin to drive this device escape power-down m ode. therefore such kind of pins should not be left floating during power-down. there are several special function registers designed to configure those i/o ports. sfr: p0m0 (p0 configuration 0) read/write address: 0x94h default: 0000-0000 bit 7 6 5 4 3 2 1 0 name p0m0.7 p0m0,6 p0m0.5 p0m0.4 p0m0.3 p0m0.2 p0m0.1 p0m0.0 sfr: p0m1 (p0 configuration 1) read/write address: 0x93h default: 0000-0000 bit 7 6 5 4 3 2 1 0 name p0m1.7 p0m1,6 p0m1.5 p0m1.4 p0m1.3 p0m1.2 p0m1.1 p0m1.0 sfr: p1m0 (p1 configuration 0) read/write address: 0x92h default: 0000-0000 bit 7 6 5 4 3 2 1 0 name p1m0.7 p1m0,6 p1m0.5 p1m0.4 p1m0.3 p1m0.2 p1m0.1 p1m0.0 sfr: p1m1 (p1 configuration 1) read/write address: 0x91h default: 0000-0000 bit 7 6 5 4 3 2 1 0 name p1m1.7 p1m1,6 p1m1.5 p1m1.4 p1m1.3 p1m1.2 p1m1.1 p1m1.0 sfr: p3m0 (p3 configuration 0) read/write address: 0xb2h default: 0000-0000 bit 7 6 5 4 3 2 1 0 name p3m0.7 p3m0,6 p3m0.5 p3m0.4 p3m0.3 p3m0.2 p3m0.1 p3m0.0 http://www..net/ datasheet pdf - http://www..net/
18 stc12c5axx technical summary sfr: p3m1 (p3 configuration 1) read/write address: 0xb1h default: 0000-0000 bit 7 6 5 4 3 2 1 0 name p3m1.7 p3m1,6 p3m1.5 p3m1.4 p3m1.3 p3m1.2 p3m1.1 p3m1.0 sfr: p4m0 (p4 configuration 0) read/write address: 0xb4h default: 0000-0000 bit 7 6 5 4 3 2 1 0 name p4m0.7 p4m0,6 p4m0.5 p4m0.4 p4m0.3 p4m0.2 p4m0.1 p4m0.0 sfr: p4m1 (p4 configuration 1) read/write address: 0xb3h default: 0000-0000 bit 7 6 5 4 3 2 1 0 name p4m1.7 p4m1,6 p4m1.5 p4m1.4 p4 m1.3 p4m1.2 p4m1.1 p4m1.0 sfr: p5m0 (p5 configuration 0) read/write address: 0xcah default: 0000-0000 bit 7 6 5 4 3 2 1 0 name p5m0.7 p5m0,6 p5m0.5 p5m0.4 p5m0.3 p5m0.2 p5m0.1 p5m0.0 sfr: p5m1 (p5 configuration 1) read/write address: 0xc9h default: 0000-0000 bit 7 6 5 4 3 2 1 0 name p5m1.7 p5m1,6 p5m1.5 p5m1.4 p5 m1.3 p5m1.2 p5m1.1 p5m1.0 configuration of i/o port p x m0 n p x m1 n port mode 0 0 quasi-bidirectional(default) 0 1 push-pull output 1 0 input only (high-impedance) 1 1 open-drain output ( x = 1 or 3 n = 7, 6, 5, 4, 3, 2, 1 or 0 ) http://www..net/ datasheet pdf - http://www..net/
stc12c5axx technical summary 19 quasi-bidirectional mode port pins in quasi-bidirectional output mode fu nction similar to the standard 8051 port pins. a quasi-bidirectional port can be used as an input and output without the need to reconfigure the port. this is possible because when the port outputs logic high, it is weakly driven, allowing an external device to pull the pin low. when the pin outputs low, it is driven strongly and able to sink a large current. there are three pull-up tran sistors in the quasi-bidi rectional output that serve different purposes. one of these pull-ups, called the ?very weak? pull-up, is turned on whenever the port register for the pin contains a logic ?1?. this very weak pull-up sources a very small current that will pull the pin high if it is left floating. a second pull-up, called the ?weak? pull-up, is turned on when the port register for the pin contains a logic ?1? and the pin itself is also at a logic ?1? level. this pull-up provides the primary source current for a quasi-bidirectional pin that is outputting a ?1?. if this pin is pulled low by the external device, this weak pull-up turns off, and only the very weak pull-up remains on. in order to pull the pin low under these conditions, the external device has to sink enough current to over-power the weak pull-up and pull the port pin below its input threshold voltage. the third pull-up is referred to as the ?strong? pull-up. this pull-up is used to speed up low-to-high transitions on a quasi-bidirectional po rt pin when the port register changes from a logic ?0? to a logic ?1?. when this occurs, the strong pull-up turns on for two cpu clocks, quickly pulling the port pin high. vdd vdd vdd port pin 2 clocks delay strong very weak weak input data port latch data http://www..net/ datasheet pdf - http://www..net/
20 stc12c5axx technical summary open-drain output the open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port pin when the port register contains logic ?0?. to use this configuration in application, a port pin must have an external pull- up, typically tied to vdd. the input path of the port pin in this configuration is the same as quasi-bidirection mode. port pin input data port latch data input-only mode the input-only configuration is a schmitt-trigge red input without any pull-up resistors on the pin. port pin input data push-pull output the push-pull output configuration has the sa me pull-down structure as both the open-drain and the quasi-bidirectional output modes, but pr ovides a continuous strong pull-up when the port register contains a logic ?1?. the push-pu ll mode may be used when more source current is needed from a port output. vdd port pin input data port latch data http://www..net/ datasheet pdf - http://www..net/
stc12c5axx technical summary 21 timer/counter stc12c5axx has two 16-bit timers, and they are named t0 and t1 . each of them can also be used as a general event counter, which counts the transition from 1 to 0. since the stc12c5axx is a risc-like mcu wh ich execute faster than traditional 80c51 mcu from other providers. based on consideration of compatib ility with traditional 80c51 mcus, the frequency of the clock source for t0 and t1 is designed to be selectable between oscillator frequency divi ded-by-12 (default) or oscillator frequency. the user can configure t0/t1 to work under mode-0, mode-1, mode-2 and mode-3. it is fully the same to a traditional 80c51 mcu. there are two sfr designed to configure timers t0 and t1 . they are tmod , tcon . the user also should take a glace of sfr auxr which decide the frequency of the clock source driving the t0 and t1 . sfr: tmod (timer mode control register) read/write address: 0x89h default: 0000-0000 bit 7 6 5 4 3 2 1 0 for timer-1 only for timer-0 only name gate c//t m1 m0 gate c//t m1 m0 gate: = gating control 0 : = (default) timer x is enabled whenever ?tr x ? control bit is set. 1 : = timer/counter x is enabled only while ?/int x ? pin is high and ? tr x ? control bit is set. c//t: = timer or counter function selector. 0 : =timer, 1 : =counter 0 : = (default) configure t x as timer use 1 : = configure t x as counter use {m1, m0}: mode select {0, 0} : = configure t x as 13-bit timer/counter {0, 1}: = configure t x as 16-bit timer/counter {1, 0} : = configure t x as 8-bit timer/counter with automatic reload capability {1, 1} : = for t0, set tl0 as 8-bit timer/counter, th0 is locked into 8-bit timer for t1, set timer/counter1 stopped http://www..net/ datasheet pdf - http://www..net/
22 stc12c5axx technical summary sfr: tcon read/write address: 0x88h default: 0000-0000 bit 7 6 5 4 3 2 1 0 name tf1 tr1 tf0 tr0 ie1 it1 ie01 it0 tf1 : = timer1 overflow flag. this bit is automatically set by hardware on t1 overflow, and will be automatically cleared by hardware when the processor vector s to the interrupt routine. tr1 : = timer1 run control bit. 0 : = (default) stop t1 counting 1 : = start t1 counting tf0 : = timer0 overflow flag. this bit is automatically set by hardware on t0 overflow, and will be automatically cleared by hardware when the processor vector s to the interrupt routine. tr0 : = timer0 run control bit. 0 : = (default) stop t0 counting 1 : = start t0 counting ie1 : = external interrupt-1 flag. this bit is automatically set by hardware on inte rrupt from the external interrupt-1, and will be automatically cleared by hardware when the proc essor vectors to the interrupt routine. it1 : = interrupt-1 type control bit. 0 : = (default) set the interrupt-1 triggered by low duty from pin ex1 1 : = set the interrupt-1 triggered by negative falling edge from pin ex1 ie0 : = external interrupt-0 flag. this bit is automatically set by hardware on inte rrupt from the external interrupt-0, and will be automatically cleared by hardware when the pr ocessor vectors to the interrupt routine. it0 : = interrupt-0 type control bit. 0 : = (default) set the interrupt-0 triggered by low duty from pin ex1 1 : = set the interrupt-0 triggered by negative falling edge from pin ex1 http://www..net/ datasheet pdf - http://www..net/
stc12c5axx technical summary 23 sfr: auxr (auxiliary register) read/write address: 0x8eh default: 00xx-xxxx bit 7 6 5 4 3 2 1 0 name t0x12 t1x12 uartm0x6 brtr s2 smod brtrx12 extram s1brs t0x12 : = t0 clock source selector 0: = (default) set the frequency of the clock source for t0 as the oscillator frequency divided-by-12. it will compatible to the traditional 80c51 mcu. 1 : = set the frequency of the clock source for t0 as the oscillator frequency. it will drive the t0 faster than a traditional 80c51 mcu. t1x12 : = t1 clock source selector 0: = (default) set the frequency of the clock source for t1 as the oscillator frequency divided-by-12. it will compatible to the traditional 80c51 mcu. 1 : = set the frequency of the clock source for t1 as the oscillator frequency. it will drive the t1 faster than a traditional 80c51 mcu. uartm0x6 : = baud rate selector of uart while it is working under mode-0 0: = (default) set the baud rate of the uart functional block as oscillator frequency divided-by-12. it will compatible to the traditional 80c51 mcu. 1 : = set the baud rate of the uart functional block as oscillator frequency divided-by-2. it will transmit/receive data faster than a traditional 80c51 mcu. brtr : = setting this bit will enable the baud-rate generator of uart2 to run. s2smod : = setting this bit can double up the baud-rate of uart2. brtrx12 : = set this bit to set the clo ck source for the uart2 is brt, or clear it to set the clock source for or the uart2 as brt/12. s1brs : = s1 baud-rate clock source selector 0: = (default) select timer-1 for baud-ra te clock source to s1 1 : = select brt for baud-rate clock source to s1 http://www..net/ datasheet pdf - http://www..net/
24 stc12c5axx technical summary 0 1 t0 or t1 pin (sampled) tl x [4:0] th x [7:0] tf x interrupt tr x 0 1 gate /int x c / / t osc/12 0 1 auxr. x osc tl x [7:0] th x [7:0] tf x interrupt 0 1 t0 or t1 pin (sampled) tr x 0 1 gate /int x c/ / t osc/12 0 1 auxr. x osc mode 0 the timer register is configured as a 13-bit register. as the count rolls over from all 1s to all 0s, it sets the timer interrupt flag tfx . the counted input is enabled to the timer when trx = 1 and either gate=0 or intx = 1. mode 0 operation is the same for timer0 and timer1. mode 1 mode1 is the same as mode0, except that the timer register is being run with all 16 bits. mode 2 mode 2 configures the timer register as an 8-bit counter (tl x ) with automatic reload. overflow from tl x does not only set tf x , but also reloads tl x with the content of th x , which is determined by user?s program. the reload leaves th x unchanged. mode 2 operation is the same for timer0 and timer1. tlx [7:0] thx [7:0] reload tf x interrupt 0 1 t0 or t1 pin (sampled) tr x 0 1 gate /int x c/ / t osc/12 0 1 auxr. x osc http://www..net/ datasheet pdf - http://www..net/
stc12c5axx technical summary 25 mode 3 timer1 in mode3 simply holds its count, the effect is the same as setting tr1 = 1. timer0 in mode 3 enables tl0 and th0 as two separate 8-bit counters. tl0 uses the timer0 control bits such like c/t, gate, tr0, int0 and tf0. th0 is locked into a timer function (can not be external event counter) and take over the use of tr1, tf1 from timer1. th0 now controls the timer1 interrupt. baud-rate generator(brt) baud-rate generator(brt) baud-rate generator and p1.0/p4.1 programmable clock output 0 1 sampled t0 pin 0 1 gate /int0 tr0 tl0 [7:0] tf0 interrupt c/ / t osc/12 0 1 osc auxr. x 0 1 th0 [7:0] tf1 interrupt tr1 osc/12 0 1 osc auxr. x brtr fosc/12 8-bit timer overflow brt to uart baud-rate generator for the uart toggle p1.0 or p4.1 brtclko fosc 0 1 s2tx12 http://www..net/ datasheet pdf - http://www..net/
26 stc12c5axx technical summary stc12c5axx is able to generate a programmable clock output on p1.0 or p4.1. when brtclko bit in wake_clko is set, brt timer overflow pulse will toggle p1.0 or p4.1 latch to generate a 50% duty clock. the frequency of clock-out is as following : brt timer overflow rate = 256 ? brt f osc 256 ? brt f osc/12 o r p1.0 / p4.1 clock output frequency = 256 ? brt f osc /2 256 ? brt f osc/24 o r http://www..net/ datasheet pdf - http://www..net/
stc12c5axx technical summary 27 interrupt there are 10 interrupt sources available in stc12c5a xx. each interrupt source can be individually enabled or disabled by setting or clearing a bit in the sfr named ie . this register also contains a global disable bit ( ea ), which can be cleared to disable all interrupts at once. each interrupt source has two corresponding bits to represent its priority. one is located in sfr named iph and the other in ip register. higher-priority interrupt will be not interrupted by lower-priority interrupt request. if two interrupt requests of different priori ty levels are received simultaneously, the request of higher priority is serviced. if interrupt requests of the same priority level are received simultaneously, an internal polling sequence determine which request is serviced. the following table shows the internal polling sequence in the same priority level and the interrupt vector address. source vector address priority within level /int0 03h 0 ( hi g hest ) timer 0 0bh 1 /int1 13h 2 timer1 1bh 3 uart 23h 4 adc 2bh 5 lvd 33h 6 pca 3bh 7 uart2 43h 8 spi 4bh 9 the external interrupt /int0, and /int1 can each be ei ther level-activated or transition-activated, depending on bits it0 and it1 in register tcon . the flags that actually generate these interrupts are bits ie0 and ie1 in tcon . when an external interrupt is generated, the flag that generated it is cleared by the hardware when the servic e routine is vectored to only if the interrupt was transition ?activated , otherwise the external requesting source is what controls the r equest flag, rather than the on-chip hardware. the timer0 and timer1 interrupts are generated by tf0 and tf1, which are set by a rollover in their respective timer/counter registers in most cases. when a timer interrupt is generated, the flag that generated it is cleared by the on-chip hardw are when the service routine is vectored to. the serial port interrupt is generated by the logical ?1 ? of ri and ti. neither of these flags is cleared by hardware when the service routine is vectored to. the service routine should poll ri and ti to determine which one to request service and it will be cleared by software. the spi interrupt is generated by the flag spif . it can only be cleared by writing a ?1? to spif bit in software . the adc interrupt is generated by the flag adc_flag . it should be cleared by software. http://www..net/ datasheet pdf - http://www..net/
28 stc12c5axx technical summary the pca interrupt is generated by the logical or of cf , ccf0 ~ ccf1 . the service routine should poll cf and ccf0 ~ ccf1 to determine which one to request service and it will be cleared by software. the low voltage detect interrupt is shared by the flag lvdf in pcon.5 register. they should be cleared by software. the uart2 interrupt is generated by the logical ?1? of s2ri and s2ti . neither of these flags is cleared by hardware when the service routine is ve ctored to. the service routine should poll s2ri and s2ti to determine which one to request service and it will be cleared by software. all of the bits that generate interr upts can be set or cleared by software, with the same result as though it had been set or cleared by hardware. in other words, interrupts can be generated or pending interrupts can be canceled in software. how does the stc12c5axx take the interrupts external interrupt pins and other interrupt sources are sampled at rising edge of each clock cycle. the samples are polled during the next clock cycle. if one of the flags was in a set condition of the first cycle, the second cycle of polling cycles will find it and the interrupt system will generate an hardware lcall to the appropriate service routine as long as it is not blocked by any of the following conditions. the 2b h interrupt is shared by the logical ?1? of adc interrupt and interrupt. neither of these flags is cleared by hardware when the service routine is vect ored to. the service routine should poll them to determine which one to request service and it will be cleared by software. the 4b h interrupt is shared by the logical ?1? of spi interrupt and interrupt. neither of these flags is cleared by hardware when the service routine is vect ored to. the service routine should poll them to determine which one to request service and it will be cleared by software. the 33 h interrupt is shared by the logical ?1? of lvd in terrupt (low-voltage detector) interrupt. neither of these flags is cleared by hardware when the service routine is vectored to. t he service routine should poll them to determine which one to request service and it will be cleared by software. the 3b h interrupt is shared by the logical ?1? of pca interrupt and interrupt. neither of these flags is cleared by hardware when the service routine is vect ored to. the service routine should poll them to determine which one to request service and it will be cleared by software. all of the bits that generate interr upts can be set or cleared by software, with the same result as though it had been set or cleared by hardware. in other words, interrupts can be generated or pending interrupts can be canceled in software. http://www..net/ datasheet pdf - http://www..net/
stc technology co.,ltd. stc12c5a08/16/32/60 8-bit micro-controller this document contains information on a new product under devel opment by stc.stc reserves the right to change or discontinue th is product without notice. 2007/12 version a1 if one of the following conditions happens, a coming interrupt will be blocked. ? an interrupt of equal or higher priority level is already in progress. ? the current cycle(polling cycle) is not the final cycle in the execution of the instruction in progress. ? the instruction in progress is reti or any write to sfrs ie , ip , ip2 , iph and ip2h registers. condition 2 ensures that the instru ction in progress will be completed before vectoring into any service routine. condition 3 ensur es that if the instruct ion in progress is reti or any access to sfrs ie , ip , ip2 , iph or ip2h , then at least one or more instruction will be executed before any interrupt is vectored to. the following content describes several sfr related to interrupt mechanism. sfr: psw (program status word) read/write address: 0xd0h default: xxxx-xx00 bit 7 6 5 4 3 2 1 0 name cy ac f0 rs1 rs0 ov f1 p cy: = carry flag. ac: = auxilliary carry flag.(for bcd operations) eadc: = interrupt controller of a/d converter (adc). 0: = (default) disable 1 : = enable f0: = flag 0.(available to the user for general purposes) rs1: = register bank select control bit 1. rs0: = register bank select control bit 0. ov : = overflow flag. f1 : = flag 1. user-defined flag. p : = parity flag. http://www..net/ datasheet pdf - http://www..net/
30 stc12c5axx technical summary sfr: ie (interrupt enable) read/write address: 0xa8h default: xxxx-xx00 bit 7 6 5 4 3 2 1 0 name ea elvd eadc es et1 ex1 et0 ex0 ea : = global interrupt controller. 0: = (default) disable all interrupts 1 : = release interrupt control to all individual interrupt controllers. elvd : = interrupt controller of low-voltage detector 0: = (default) disable 1 : = enable eadc: = interrupt controller of a/d converter (adc). 0: = (default) disable 1 : = enable es: = interrupt controller of universal as ynchronous receiver/transmitter (uart). 0: = (default) disable 1 : = enable et1: = interrupt controller of timer-1 interrupt. 0: = (default) disable 1 : = enable ex1: = interrupt controller of external interrupt-1. 0: = (default) disable 1 : = enable et0: = interrupt controller of timer-0 interrupt. 0: = (default) disable 1 : = enable ex0: = interrupt controller of external interrupt-0. 0: = (default) disable 1 : = http://www..net/ datasheet pdf - http://www..net/
stc12c5axx technical summary 31 enable sfr: ip (interrupt priority low) read/write address: 0xb8h default: 0000-0000 bit 7 6 5 4 3 2 1 0 name ppca plvdi padc ps pt1 px1 pt0 px0 ppca: = if set, set priority for pca interrupt higher plvd: = if set, set priority for low voltage interrupt higher padc: = if set, set priority for adc interrupt highe ps: = if set, set priority for seri al port interrupt higher(uart) pt1: = if set, set priority fo r timer1 interrupt higher px1: = if set, set priority for external interrupt 1 higher pt0: = if set, set priority for timer0 interrupt higher px0: = if set, set priority for external interrupt 0 higher sfr: iph (interrupt priority high) read/write address: 0xb7h default: 0000-0000 bit 7 6 5 4 3 2 1 0 name ppcah plvdh padch psh pt1h px1h pt0h px0h ppcah: = if set, set priority for pca interrupt higher plvdh: = if set, set priority for low voltage interrupt higher padc: = if set, set priority fo r adc interrupt higher psh: = if set, set priority for serial port interrupt higher (uart) pt1h: = if set, set priority for timer1 interrupt higher px1h: = if set, set priority for ex ternal interrupt 1 higher pt0h: = if set, set priority for timer0 interrupt higher px0h: = if set, set priority for ex ternal interrupt 0 higher http://www..net/ datasheet pdf - http://www..net/
stc technology co.,ltd. stc12c5a08/16/32/60 8-bit micro-controller this document contains information on a new product under devel opment by stc.stc reserves the right to change or discontinue th is product without notice. 2007/12 version a1 sfr: ip2 (interrupt priority high) read/write address: 0xb6h default: 0000-0000 bit 7 6 5 4 3 2 1 0 name pspi ps2 sfr: ip2h (interrupt priority high) read/write address: 0xb7h default: 0000-0000 bit 7 6 5 4 3 2 1 0 name pspih ps2h ip and iph are combined to form 4-level priority interrupt as the following table. {iph.x, ip.x} priority level 11 1 (highest) 10 2 01 3 00 4 http://www..net/ datasheet pdf - http://www..net/
stc12c5axx technical summary 33 interrupt control block /int0 ie0 ie1 /int1 tf0 tf1 ri ti ie, xicon,auxie registers ip,ip2,iph,iph2 registers highest priority level interrupt lowest priority level interrupt interrupt polling sequenc e global enable (ie.7) individual enable cf ecf ccf1 eccf1 ccf0 eccf0 ccf2 eccf2 ie. 0 ie. 1 ie. 2 ie. 3 ie. 4 ie. 5 ie2.1 ie.5 ecf ie2.0 ie.6 tf2 exf2 spif adc_flag s2ri s2ti epof pof elvd lvdf http://www..net/ datasheet pdf - http://www..net/
34 stc12c5axx technical summary watch dog timer the watch dog timer in stc12c5axx consists of an 8-bit pre-scalar timer and a 15-bit timer. the timer is one-time enabled by setting en_wdt. clearing enw can not stop wdt counting. when the wdt is enabled, software sh ould always reset the timer by writing 1 to clr_wdt bit before the wdt overflows. if stc12c 5axx is out of control by any disturbance, that means the cpu can not run the software normally, then wdt may miss the ?writing 1 to clr_wdt? and overflow w ill come. wdt overflow reset the cpu to restart. ps2 ps1 ps0 - en_ wdt clr_ wdt idl_ wdt wdt_ flag 1/256 1/128 1/64 1/32 1/16 1/8 1/4 1/2 8-bit prescalar 15-bit timer idle fosc/12 wdt_contr to make good use of the watch-dog-timer, the user should take notice on sfr wdt_contr . sfr: wdt_contr (wdt control register) c1h read/write address: 0xc1h default: 0000-0000 bit 7 6 5 4 3 2 1 0 name wdt_flag en_wdt clr_wdt idl_wdt ps2 ps1 ps0 wdt_flag: = when wdt overflows, this bit is set. it can be cleared by software. en_wdt: = control bit to enable watch-dog-timer. (one-time enabled, can not be disabled) 0: = (default) disable watch dog timer 1 : = enable watch dog timer start counting clr_wdt: = set this bit to recoun t wdt. hardware will auto matically clea r this bit. http://www..net/ datasheet pdf - http://www..net/
stc12c5axx technical summary 35 idl_wdt: = behavior controller of the wdt while the device is put under idle 0: = (default) stop watch dog timer counting 1 : = keep watch dog timer counting (so further reset could happen) {ps2, ps1, ps0} : selector of the wdt pre-scalar output. { 0, 0, 0 } : = set the pre-scaling value 2 { 0, 0, 1 } : = set the pre-scaling value 4 { 0, 1, 0 } : = set the pre-scaling value 8 { 0, 1, 1 } : = set the pre-scaling value 16 {1 , 0, 0 } : = set the pre-scaling value 32 { 1, 0, 1 } : = set the pre-scaling value 64 { 1, 1, 0 } : = set the pre-scaling value 128 { 1, 1, 1 } : = set the pre-scaling value 256 http://www..net/ datasheet pdf - http://www..net/
36 stc12c5axx technical summary baud rate ( for mode 2) = 2 smod 64 x fosc universal asynchronous serial port (uart) the serial port of stc12cxx is duplex. it can transmit and receive simultaneously. the receiving and transmitting of the serial port share the same sfr sbuf , but actually there are two sbuf registers implemented in the chip, one is for transmitting and the other is for receiving. the serial port can be operated in 4 different modes. mode 0 generally, this mode purely is used to ex tend the i/o features of this device. operating under this mode, the device receives t he serial data or transmits the serial data via pin rxd, while there is a clock stream sh ifted via pin txd which makes convenient for external synchronization. an 8-bit data is serially transmitted/received with lsb first. the baud rate is fixed at 1/12 t he oscillator frequency. if auxr .5 ( urm0x6 ) is set, the baud rate is 1/2 oscillator frequency. mode1 a 10-bits data is serially transmitted through pin txd or received through pin rxd. the frame data includes a start bit ( 0 ), 8 data bits and a stop bit ( 1 ). after finishing a receiving, the device will keep the stop bit in rb8 which from srf scon . mode2 an 11-bit data is serially transmitted through txd or received through rxd . the frame data includes a start bit ( 0 ), 8 data bits, a programmable 9th bit and a stop bit (1). on transmit; the 9th data bit comes from tb8 in sfr scon . on receive; the 9th data bit goes into rb8 in scon . the baud rate is programmable, and permitted to be set either 1/32 or 1/64 the oscillator frequency. baud rate ( for mode 1) = 2 smod 32 x (timer-1 overflow rate) http://www..net/ datasheet pdf - http://www..net/
stc12c5axx technical summary 37 mode3 mode 3 is the same as mode 2 except the baud rate is variable. in all four modes, transmission is initiated by any instruction that uses sbuf as a destination register. reception is initiat ed in mode 0 by the condition ri = 0 and ren = 1 . reception is initiated in the other modes by the incoming start bit with 1 -to- 0 transition if ren = 1 . there are several sfrs related to serial port configuration described as following. sfr: scon (serial control) read/write address: 0x98h default: 0000-0000 bit 7 6 5 4 3 2 1 0 name sm0/fe sm1 sm2 ren tb8 rb8 ti ri fe: = frame error bit this bit is set by the receiver when an invalid st op bit is detected. the fe bit is not cleared by valid frames but should be cleared by software. the smod0 bit must be set to enable access to the fe bit. {sm0 , sm1}: = used to set operating mode of the serial port. {0 , 0 }: = set the serial port operate under mode 0 {0 , 1 } : = set the serial port operate under mode 1 {1 , 0 } : = set the serial port operate under mode 2 {1 , 1 } : = set the serial port operate under mode 3 sm2: = enable the automatic address recognition feature in mode 2 and 3. if sm2 = 1 , ri will not be set unless the received 9th data bit is 1, indicating an address, and the received byte is a given or broadcast address. in mode1, if sm2=1 then ri will not be set unless a valid stop bit was received, and the received byte is a given or broadcast address. ren: = enable the serial port reception. 0: = (default) disable the serial port reception. 1 : = enable the serial port reception. tb8: = the 9th data bit, which will be transmitted in mode 2 and mode 3. rb8: = in mode 2 and 3, the received 9th data bit will be put into this bit. ti: = transmitting done flag. after a transmitting has been finished, the hardware will set this baud rate ( for mode 3) = 2 smod 32 x (timer-1 overflow rate) http://www..net/ datasheet pdf - http://www..net/
38 stc12c5axx technical summary bit. ri: = receive done flag. after reception has been finished, the hardware will set this bit. http://www..net/ datasheet pdf - http://www..net/
stc12c5axx technical summary 39 bit[ i ] of compared byte = ( saden [ i ] == 1 )? saddr [ i ] : x ri = (sm2 == 1 ) && (sbuf == compared byte ) && (rb8 == 1 ) sfr: sbuf (serial buffer) read/write address: 0x99h default: 00 00-0000 bit 7 6 5 4 3 2 1 0 name frame error detection when used for frame error detect, the uart looks for missing stop bits in the communication. a missing bit will set the fe bit in the scon regi ster. the fe bit shares the scon.7 bit with sm0 and the function of scon.7 is determined by pcon.6 (smod0). if smod0 is set then scon.7 functions as fe. scon.7 functions as sm0 when smod0 is cleared. when used as fe, scon.7 can only be cleared by software. automatic address recognition there is an extra feature makes the devic e convenient to act as a master, which communicates to multiple slaves simultaneously. it is really automatic address recognition . there are two sfr saddr and saden implemented in the device. the user can read or write both of them. finally, the hardware will make use of these two sfr to ?generate? a ?compared byte?. the formula specifies as following. for example: set saddr = 11000000b set saden = 11111101b ? the achieved ?compared byte? will be ?110000x0? ( x means don?t care) for another example: set saddr = 11100000b set saden = 11111010b ? the achieved ?compared byte? will be ?11100x0x? after the generic ?compared byte? has been work ed out, the stc12cxx will make use of this byte to determine how to set the bit ri in sfr scon . normally, an uart will set bit ri whenever it has done a byte rece ption; but for the uart in the stc12cxx, if the bit sm2 is set, it will set ri according to the following formula. in other words, not all data reception will respond to ri, while specific data does. by setting the saddr and the saden, the user can filter out those data byte that he doesn?t like to care. this feature brings great help to reduce software overhead. the above feature adapts to the serial port when operated in mode1, mode2, and mode3. dealing with mode 0, the user can ignore it. http://www..net/ datasheet pdf - http://www..net/
stc technology co.,ltd. stc12c5a08/16/32/60 8-bit micro-controller this document contains information on a new product under devel opment by stc.stc reserves the right to change or discontinue th is product without notice. 2007/12 version a1 secondary universal asynch ronous serial port (s2) s2 is the secondary uart of stc12c5axx whose func tion is fully the same with the major uart excepting that no enhanced function included. an addi tional baud-rate generator (s2brt) is available in s2 to simplify the baud-rate generation and release timer1 for use in other purposes. the additional baud-rate generator can also be configured to provide a programmable clock output on p1.0/p4.1. combined with timer1 and brt, stc12c5axx will be able to provide three individual programmable clock outputs on thr ee general-purpose i/o pins, respectively. mode 0 serial data enters and exits through pin rxd2 (p1.2/p4.2), and pin txd2 (p1.3/p4.3) outputs the shift clock. eight data bits are transmitted/received with the lsb first. the baud rate is fixed at 1/12 the oscillator frequency. regardless of baud-rate generatio n, the operation in mode 0 for s2 uart is the same as the major uart in mode 0. mode1 10 bits are transmitted through pin txd2 or received through pin rxd2 . the frame data includes a start bit( 0 ), 8 data bits and a stop bit( 1 ). one receive, t he stop bit goes into s2rb8 in sfr s2con . the baud rate is determined by the brt overflow rate. regardl ess of baud-rate generation, the operation in mode 1 for s2 uart is the same as the standard uart in mode 1. mode2 11 bits are transmitted through pin txd2 or received through pin rxd2 . the frame data includes a start bit( 0 ), 8 data bits, a programmable 9th bit and a stop bit( 1 ). on transmit, the 9th data bit comes from s2tb8 in s2con . on receive, the 9th data bit goes into s2rb8 in s2con . the baud rate is programmable to either 1/32 or 1/64 the oscillator frequency. the operation in mode 2 for s2 is the same as the major uart in mode 2. baud rate ( for mode 2) = 2 s2smod 64 x brt baud rate ( for mode 1) = 2 s2smod 32 x (brt timer overflow rate) http://www..net/ datasheet pdf - http://www..net/
stc12c5axx technical summary 41 mode3 mode 3 is the same as mode 2 except the baud rate is variable. the user can redirect functional pins rxd2 and rxd2 from pins p1.2 and p1.3 to pins p4.2 and p4.3 by setting bit s2p4 in sfr auxr1 . there are several special function registers whic h should be understood by users before using the secondary uart. sfr: s2con read/write address: 0x9ah default: 0000-0000 bit 7 6 5 4 3 2 1 0 name s2sm0 s2sm1 s2sm2 s2ren s2tb8 s2rb8 s2ti s2ri { s2sm0 , s2sm1 } := used to set operating mode of the serial port. { 0, 0 } := set the serial port operate under mode 0(8-bit shift register) { 0, 1 } := set the serial port operate under mode 1(8-bit uart) { 1, 0 } := set the serial port operate under mode 2(9-bit uart) { 1, 1 } := set the serial port operate under mode 3(9-bit uart) s2sm2 := enable the automatic address recognition feature in mode 2 and 3. if sm2 = 1 , ri will not be set unless the received 9th data bit is 1, indicating an address, and the received byte is a given or broadcast addre ss. in mode1, if sm2=1 then ri will not be set unless a valid stop bit was received, and the received byte is a given or broadcast address. s2ren := enable the serial port reception. 0 := (default) disable the secondary serial port reception. 1 := enable the secondary serial port reception. s2tb8 := the 9th data bit, which will be transmitted in mode 2 and mode 3. baud rate ( for mode 3) = 2 s2smod 32 x (brt timer overflow rate) http://www..net/ datasheet pdf - http://www..net/
42 stc12c5axx technical summary s2rb8 := in mode 2 and 3, the received 9th data bit will be put into this bit. s2ti := transmitting done flag. after a transmitting has been finished, the hardware will set this bit. s2ri := receive done flag. after reception has been finished, the hardware will set this bit. sfr: s2buf read/write address: 0x9bh default: 0000-0000 bit 7 6 5 4 3 2 1 0 name sfr: brt read/write address: 0x9ch default: 0000-0000 bit 7 6 5 4 3 2 1 0 name it is used as the reload register for gene rating the baud-rate of the secondary uart only sfr: auxr read/write address: 0x9bh default: 0000-0000 bit 7 6 5 4 3 2 1 0 name t0x12 t1x12 uartm0x6 brtr s2smod brtx12 extram s1brs t0x12 := set this bit to set the clock sour ce for timer 0 is fosc, or clear it to set the clock source for timer 0 as fosc/12. t1x12 := set this bit to set the clock sour ce for timer 0 is fosc, or clear it to set the clock source for timer 1 as fosc/12. uartm0x6 := set this bit to set the clock sour ce for the major uart is fosc/2, or clear it to set the clock source for or the major uart as fosc/12. brtr := setting this bit will enable the baud-rate generator of secondary uart to run. s2smod := setting this bit can double up the baud-rate of secondary uart. brtx12 := http://www..net/ datasheet pdf - http://www..net/
stc12c5axx technical summary 43 set this bit to set the clock source for the second ary uart is brt, or clear it to set the clock source for or the secondary uart as brt/12. extram := 0 : = on-chip auxiliary ram is enabled and located at the address 0x0000 to 0x03ff. for address above 0x03ff, external ram becomes the target automatically. 1 : = on-chip auxiliary ram is always disabled.. s1brs := set this bit to set the clock sour ce for the uart is brt, or clear it to set the clock source for or the uart as timer-1. sfr: wake_clko read/write address: 0x8fh default: 0000-0x00 bit 7 6 5 4 3 2 1 0 name pca wakeup rxd_pin_ ie t1_pin_ ie t0_pin_ ie lvd_ wake brtclko t1clko t0clko wakeup : = if this bit has been enabled, the pca interrupt can wake-up the device from power-down mode. rxd_pin_ie: if this bit has been enabled, the rxd interrupt can wake-up the device from power-down mode.. t1_pin_ie : = if this bit has been enabled, the timer-1 interr upt can wake-up the device from power-down mode.. t0_pin_ie : = if this bit has been enabled, the timer-0 interrupt can wake-up the device from power-down mode. lvd_wake : = setting the bit, the lvd interrupt can wake-up the device from power-down mode. 0 : = (default) 1: = brtclko := setting this bit can enable brt clock output on p1.0. the frequency of the output clock will be set as (brt overflow rate / 2 ) http://www..net/ datasheet pdf - http://www..net/
44 stc12c5axx technical summary t1clko := setting this bit can enable timer 0 clock output on p3.5. the frequency of the output clock will be set as ( timer 1 overflow rate / 2 ) tclko := setting this bit can enable timer 0 clock output on p3.4. the frequency of the output clock will be set as ( timer 0 overflow rate / 2 ) http://www..net/ datasheet pdf - http://www..net/
stc12c5axx technical summary 45 programmable counter array (pca) the programmable counter array is a special 16-bit ti mer that has two 16-bit capture/compare modules associated with it. each of the modules can be programmed to operate in one of four modes: z rising and/or falling edge capture (calculator of duty length for high/low pulse) z software timer z high-speed output z pulse width modulator each module has a pin associated with it in port 1. module-0 is connected to pin p1.3, module-1 to pin p1.4. the pca timer is a common time base for all two modules and can be programmed to run at 1/12 the oscillator frequency, 1/2 the oscillator frequency, the timer-0 overflow or the input on pin eci (p3.4). the timer count source is determined from cps1 and cps0 bits in the sfr cmod . module-0 capture/compare register module-1 capture/compare register pca timer/counter 16 bit p1.3/cex0/ pca0/pwm0 p1.4/cex1/ pca1/pwm1 programmable counter array in the cmod sfr, there are two additional bits asso ciated with the pca. on of them is cidl which determines if to stop the pca while the m cu is put under idle, the other bit is ecf which controls if to pass the interrupt from pca into the mcu. the ccon sfr contains the run control bit for pca and several flags for the pca timer and each module. to start the pca counting, the cr bit ( ccon .6) must be set by software; oppositely clearing bit cr will shut off the pca. there is a bit named cf in sfr ccon . the cf bit ( ccon .7) will be set when the pca timer overflows, and an interrupt will be generated if the ecf ( cmod .0) is set. the cf bit can only be cleared by software. there are two bits named ccf0 and ccf1 in sfr ccon . the ccf0 and ccf1 serve as flags for module-0 and module-1 respec tively. they are set by hardware when either a match or a capture occurs. these flags also can only be cleared by software. http://www..net/ datasheet pdf - http://www..net/
46 stc12c5axx technical summary ch cl fosc/12 fosc/2 timer0 overflow external input eci (p3.4) cps1 cps0 ecf -- -- cidl cmod - ccf1 ccf0 cr - -- cf ccon idle pca interrupt to pca module 16-bit counter pca timer/counter sfr: cmod (pca mode control register) read/write address: 0xd9fh default: 0xxx-x000 bit 7 6 5 4 3 2 1 0 name cidl cps1 cps0 ecf cidl := behavior control of the pca. 0 := (default) disable counting of the pca counter whil e the mcu is put under idle state. 1 := enable counting of the pca counter whil e the mcu is put under idle state. { cps1 , cps0 } := used to select the clocking source for pca counter { 0, 0 } := set the frequency of the pca counter clock source as oscillator?s frequency over 12 { 0, 1 } := set the frequency of the pca counter clock source as oscillator?s frequency over 2 { 1, 0 } := set the pca counter clock source as timer-0 overflow { 1, 1 } := set the pca counter clock source as pin eci(pin p3.4) ecf := control bit of deciding if to pass interrupt from pca timer overflow to the mcu 0 := (default) inhibit the interrupt from pca timer to the mcu 1 := permit the interrupt from pca timer to the mcu http://www..net/ datasheet pdf - http://www..net/
stc technology co.,ltd. stc12c5a08/16/32/60 8-bit micro-controller this document contains information on a new product under devel opment by stc.stc reserves the right to change or discontinue th is product without notice. 2007/12 version a1 sfr: ccon (pca counter control rregister) read/write address: 0xd8fh default: 0xxx-x000 bit 7 6 5 4 3 2 1 0 name cf cr ccf1 ccf0 cf := pca counter overflow flag this bit must be set by hardware itse lf. it can be cleared by software program. cr := pca run control bit 0 := (default) disable counting of the pca counter 1 := start counting of the pca counter ccf1 := module-1 interrupt flag this bit must be set by hardware itself when a match or capture from module-1 occurs. it can be cleared by software program. a match means the value of the pca counter equals the value of t he capture/compare register in the module-1. a capture means a specific edge from cex1 happens, so the capture/compare register latches the value of the pca counter, and the ccf1 is set. ccf0 := module-0 interrupt flag this bit must be set by hardware itself when a match or capture from module-0 occurs. it can be cleared by software program. each module in the pca has a special function register associated with it, ccapm0 for module0 and ccapm1 for module-1. the register contains the bits that control the mode in which each module will operate. the eccf n bit controls if to pass the interrupt from ccf n flag in the ccon sfr to the mcu when a match or compare occurs in the associated module. pwm n enables the pulse width modulation mode. the tog n bit when set causes the pin cex n output associated with the module to t oggle when there is a match between the pca counter and the module?s capture/compare register . the match bit( mat n ) when set will cause the ccf n bit in the ccon register to be set when there is a match between the pca counter and the module?s capture/compare register . the next two bits capn n and capp n determine the edge type that a capture input will be active on. the capn n bit enables the negative edge, and the capp n bit enables the positive edge. if both bits are set, both edges will be enabled and a capture will occur for either transition. the bit ecom n when set enables the comparator function. http://www..net/ datasheet pdf - http://www..net/
48 stc12c5axx technical summary sfr: cl (pca base counter low byte) read/write address: 0xe9h default: 0000-0000 bit 7 6 5 4 3 2 1 0 name sfr: ch (pca base counter high byte) read/write address: 0xf9h default: 00000-0000 bit 7 6 5 4 3 2 1 0 name sfr: ccap0l (low byte of pca module-0 compare/capture register) read/write address: 0xeah default: 0000-0000 bit 7 6 5 4 3 2 1 0 name sfr: ccap0h (high byte of pca module-0 compare/capture register) read/write address: 0xfah default: 0000-0000 bit 7 6 5 4 3 2 1 0 name sfr: ccap1l (low byte of pca module-1 compare/capture register) read/write address: 0xebh default: 0000-0000 bit 7 6 5 4 3 2 1 0 name sfr: ccap1h (high byte of pca module-1 compare/capture register) read/write address: 0xfbh default: 0000-0000 bit 7 6 5 4 3 2 1 0 name http://www..net/ datasheet pdf - http://www..net/
stc technology co.,ltd. stc12c5a08/16/32/60 8-bit micro-controller this document contains information on a new product under devel opment by stc.stc reserves the right to change or discontinue th is product without notice. 2007/12 version a1 sfr: ccapm0 (pca modul-0 mode register) read/write address: 0xdah default: x000-0000 bit 7 6 5 4 3 2 1 0 name ecom0 capp0 capno mat0 tog0 pwm0 eccf0 sfr: ccapm1 (pca modul-1 mode register) read/write address: 0xdbh default: x000-0000 bit 7 6 5 4 3 2 1 0 name ecom1 capp1 capn1 mat1 tog1 pwm1 eccf1 ecom n := used to determine if enable comparator 0 := (default) disable the comparator function 1 := enable the comparator function capp n : = configure the module- n ?s register to latch the pca counter on positive edge of exi n or not 0 := (default) configure the module- n ?s register not to latch the pca counter on capp n posedge. 1 := configure the module- n ?s register to latch the pca counter on capp n posedge. capn n : = configure the module- n ?s register to latch the pca counter on negative edge of exi n or not 0 := (default) configure the module- n ?s register not to latch the pca counter on pin capp n negedge. 1 := configure the module- n ?s register to latch the pca counter on pin capp n negedge. mat n : = used to determine if set the bit ccf n in sfr ccon while a match from module- n occurs. 0 := (default) don?t set the bit ccf n while a match occurs between the pca counter and module- n ?s register. 1 := set the bit ccf n while a match occurs between the pca counter and module- n ?s register. tog n : = toggle the output pin 0 := (default) don?t toggle the pin cex n while a match occurs between the pca counter and module- n ?s register. 1 := toggle the pin cex n while a match occurs between the pca counter and module- n ?s register. pwm n : = enable plus width modulation mode n . 0 := (default) http://www..net/ datasheet pdf - http://www..net/
50 stc12c5axx technical summary inhibit the pwm functionality fr om module-n output to pin pwm n 1 := enable the pin pwm n as the output of the pwm functionality from module- n http://www..net/ datasheet pdf - http://www..net/
stc12c5axx technical summary 51 eccf n : = enable the ccf n flag in the ccon sfr to generate an interrupt. 0 := (default) inhibit the interrupt( ccf n ) from module- n to the mcu 1 := permit the interrupt( ccf n ) from module- n to the mcu configure pca module ecom n capp n capn n mat n tog n pwm n eccf n module function 0 0 0 0 0 0 0 no operation x 1 0 0 0 0 x 16-bit capture by a positive-edge trigger on cex n x 0 1 0 0 0 x 16-bit capture by a negative trigger on cexn x 1 1 0 0 0 x 16-bit capture by a transition on cexn 1 0 0 1 0 0 x 16-bit software timer 1 0 0 1 1 0 x 16-bit high speed output 1 0 0 0 0 1 0 8-bit pwm pca capture mode to use one of the pca modules in the capture mode, one or both of bits capp n and capn n in sfr ccapm n should be set. the external cex n input for the module is sampled for a transition. when a valid transition occurs, t he pca hardware loads the value of the pca counter register( ch and cl ) into the module?s capture registers( ccap n h and ccap n l ). if the bit ccf n for the module in the sfr ccon and the bit eccf n in the sfr ccapm n are set then an interrupt will be generated. ch cl cex n togn pwmn eccfn ecomn cappn capnn matn - md n con - ccf1 ccf0 cr - -- cf ccon pca interrupt pca capture mode ccap n h ccap n l capture 0000 http://www..net/ datasheet pdf - http://www..net/
52 stc12c5axx technical summary 16-bit software timer mode the pca modules can be used as software timers by setting both the ecom n and mat n bits in the ccapm n register. the pca timer will be compared to the module?s capture registers and when a match occurs an interrupt will be generated if the ccf n and eccf n bits for the module are both set. high speed output mode in this mode the cex n output (port latch) associated wi th the pca module will toggle each time a match occurs between the pca counter and the module?s capture registers. to activate this mode the tog n , mat n , and ecom n bits in the sfr ccapm n must be set. pulse width modulator mode all of the pca modules can be used as pw m outputs. the frequency of the output depends on the pca counter. all of the modules will have the same frequency of output because they all share the pca counter. the duty cycle of each module is independently variable using the module?s capture register ccap n l[7:0] and bits epc n l in sfr pcapwm n . when the value of the sfr cl is less than the value in the module?s { epcnl , ccap n l [7:0] }, the output will be low. when it is equal to or great er than, the output will be high. when cl overflows from ff h to 00 h , { epcnl , ccap n l [7:0] } is reloaded with the value in { epcnh , ccap n h [7:0] }. that allows smoothly updating the pwm duty without glitches. the bits pwm n and ecom n bits in the ccapm n must be set to enable the pwm mode. sfr: pca_pwm0 (pca pwm0 auxiliary register) read/write address: 0xf2h default: 0000-0000 bit 7 6 5 4 3 2 1 0 name epc0h epc0l sfr: pca_pwm1 (pca pwm1 auxiliary register) read/write address: 0xf3h default: 0000-0000 bit 7 6 5 4 3 2 1 0 name cf cr epc1h epc1l epc n l: = concatenated with ccap n l , used to control the duty of the pwm output the bit epc n l is going to be combined with ccap n l to form a 9-bit data which will be compared with pca counter low byte cl , so to determine the duty of the module- n ?s pwm output. if { cl[7:0] } < { epc n l, ccap n l[7:0]} , pwm output low else pwm output high epc n h: = reloaded value of epcnl while cl [7:0] counts from ff h to 00 h http://www..net/ datasheet pdf - http://www..net/
stc12c5axx technical summary 53 ccap n h ccap n l togn pwmn eccfn ecomn cappn capnn matn - ccapm n - ccf1 ccf0 cr - -- cf ccon pca interrupt pca software timer mode 16-bit comparator 00 ch cl match 00 enable 01 write to ccapnl write to ccapnh to ccfn ccap n h ccap n l togn pwmn eccfn ecomn cappn capnn matn - ccapm n - ccf1 ccf0 cr - -- cf ccon pca interrupt pca high-speed ouput mode 16-bit comparator 10 ch cl match 00 enable 01 write to ccapnl write to ccapnh to ccfn cexn toggle http://www..net/ datasheet pdf - http://www..net/
54 stc12c5axx technical summary ccap n h epc n h ccap n l epc n l 9-bit comparator cl 0 cl overflow ecomn cappn capnn matn togn pwmn eccfn 0000 0 enable 0 1 cex n ccapm n pca pwm mode {0, cl[7:0]} < {epc n l, ccap n l[7:0]} {0, cl[7:0]} >= {epc n l, ccap n l[7:0]} http://www..net/ datasheet pdf - http://www..net/
stc technology co.,ltd. stc12c5a08/16/32/60 8-bit micro-controller this document contains information on a new product under devel opment by stc.stc reserves the right to change or discontinue th is product without notice. 2007/12 version a1 serial peripheral interface(spi) the device provides another high-speed serial communi cation interface, the spi interface. the spi is a full-duplex, high-speed, synchronous communication bus with two operation modes: master mode and slave mode. up to 3mbit/s can be supported in either master or slave mode under the fosc=12mhz. two status flags are provided to signal the tr ansfer completion and write-collision occurrence. there are three pins implementing the spi functionality, one of them is sclk(p1. 7), next is miso(p1.6), the other is mosi(p1.5). an extra pin ss(p1.4) is designed to configure the spi to run under master or slave mode. data flows from master to slave via mosi (master out slave in) pin and flows from slave to master via miso(master in slave out) pin. the sc lk plays as an output pin when the device works under master mode, while as an input pin when the device works under slave mode. if the spi system is disabled, i.e. spen ( spctl .6)=0, these pins are configured as general-purposed i/o port(p1.4 ~ p1.7). two devices with spi interface communicate with each other via one synchronous clock signal , one input data signal, and one output data signal. there ar e two concerns the user could take care, one of them is latching data on the n egative edge or positive edge of the clock signal which named polarity , the spictl spr0 spr1 cpha cpol mstr dord spen ssig spi control shift in register shift out register clock divider i/o control spistat - - - - - - wcol spif p1.6 (miso) p1.5 (mosi) p1.7 (spiclk) p1.4 (ss) 4, 16, 64 128 fosc spi block diagram http://www..net/ datasheet pdf - http://www..net/
56 stc12c5axx technical summary other is keeping the clock signal low or high while the device idle which named phase . permuting those states from polarity and phase , there could be four modes formed, they are spi-mode-0 , spi-mode-1 , spi-mode-2 , spi-mode-3 . many device declares that they meet spi mechanism, but few of them are adaptive to all four modes. the stc12c5axx is a dev ice flexible to be configured to communicate to another device with mode-0 , mode-1 , mode-2 or mode-3 spi, and play part of master and slave . there is a sfr named spictl designed to c onfigure the spi behavior of the device. sfr: spctl (spi control register) read/write address: 0x85h default: 0000-0000 bit 7 6 5 4 3 2 1 0 name ssig spen dord mstr cpol cpha spr1 spr0 ssig := used to determine if ignore the pin ss 0 := (default) reserve the function of pin ss 1 := ignore the ss pin function spen := enable the spi 0 := (default) disable the spi function. all related pins play as general-purposed i/o ports. 1 := enable the spi function. dord := data order 0 := (default) transmit/receive the msb of the data byte first. 1 := transmit/receive the lsb of the data byte first. mstr := set to master mode 0 := (default) set the spi to play as slave part. 1 := set the spi to play as master part. cpol := clock polarity 0 := (default) set the spclk as low while the communication is kept idle. that implies the leading edge of the clock is the rising edge, and the trailing edge is the falling edge. http://www..net/ datasheet pdf - http://www..net/
stc12c5axx technical summary 57 1 := set the spclk as high while the communication is kept idle. that implies the leading edge of the clock is the falling edge, and t he trailing edge is the falling rising edge. cpha := clock phase 0 := (default) data is driven when pin ss is low and changes on the trailing edge of spclk, and is sampled on the leading edge. ( this setting is only valid while ssig==0 .) 1 := data is driven on the leading edge of spc lk, and is sampled on the trailing edge. {spr1, spr0} := spi clock rate selector {0,0} := (default) set the clock rate of the spi as the fr equency of the clock source over 4. {0,1} := set the clock rate of the spi as the fr equency of the clock source over 16. {1,0} := set the clock rate of the spi as the fr equency of the clock source over 64. {1,1} := set the clock rate of the spi as the frequ ency of the clock source over 128. there are two extra sfrs make re lation with spi application. sfr: spdat (spi data register) read/write address: 0x86h default: 0000-0000 bit 7 6 5 4 3 2 1 0 name the sfr spdat holds the data to be transmitted or the data received. sfr: spstat (spi state register) read/write address: 0x84h default: 00xx-xxxx bit 7 6 5 4 3 2 1 0 name spif wcol spif := spi transfer completion flag. when a serial transfer finishes, the spif bit is set and an interrupt is generated if both the espi(auxr.3) bit and the ea(ie.7) bit are set. if ss is an input and is driven low when spi is in master mode with ssig=0, spif will also be set to signal the ?mode change?. the spif is cleared in software by ?writing 1 to this bit?. wcol := spi write collision flag http://www..net/ datasheet pdf - http://www..net/
58 stc12c5axx technical summary the wcol bit is set if the spi data register spidat is written during a data transfer. the wcol flag is cleared in software by ?writing 1 to this bit?. configure the device to master / slave mode spen ssig ss mstr mode miso mosi spiclk remark 0 x x x spi disable gpi/o gpi/o gpi/o spi is disabled. 1 0 0 0 active salve output input input selected as slave 1 0 1 0 inactive slave hi-z input input not selected. 1 0 0 1 0 slave output input input convert from master to slave 1 0 1 1 master input output output spclk depends on cpol 1 1 x 0 slave output input input slave 1 1 x 1 master input output output master http://www..net/ datasheet pdf - http://www..net/
stc12c5axx technical summary 59 typical connection master/slave slave/master miso miso mosi mosi spclk spclk ss ss spi dual device configuarion, where either can be a master or a slave master slave #1 miso miso mosi mosi spclk spclk ss port pin 1 spi single master multiple slaves configurartion slave #2 miso mosi spclk ss port pin 2 master slave miso miso mosi mosi spclk spclk ss port pin spi single master single slave configurartion http://www..net/ datasheet pdf - http://www..net/
60 stc12c5axx technical summary communication in spi, transfers are always initiated by the master. if the spi is enabled( spen =1) and selected as master, any instruction that use spi data register spidat as the destination will starts the spi clock generator and a data transfer. the data will start to appear on mosi about one half spi bit-time to one spi bit-time after it. before starting the transfer, the master may select a slave by driving the ss pin of the corresponding device low. data written to the spdat register of the master shifted out of mosi pin of the master to the mosi pin of the slave. and at the same time the data in spdat register of the selected slave is shifted out of miso pin to the miso pin of the master. during one byte transfer, data in the master and in the slave is interchanged. after shifting one byte, the transfer completion flag( spif ) is set and an interrupt will be created if the spi interrupt is enabled. if spen =1, ssig =0, ss pin=1 and mstr =1, the spi is enabled in master mode. before the instruction that use spdat as the destination register, the master is in idle state and can be selected as slave device by any other master drives the idle master ss pin low. once this happened, mstr bit of the idle master is cleared by hardware and changes its state a selected slave. user software should always check the mstr bit. if this bit is cleared by the mode change of ss pin and the user wants to continue to use the spi as a master later, the user must set the mstr bit again, otherwise it will always stay in slave mode. the spi is single buffered in transmit direction and double buffered in receive direction. new data for transmission can not be written to the shift register until the previous transaction is complete. the wcol bit is set to signal data collision when the data register is written during transaction. in this case, the data currently being transmitted will continue to be transmitted, but the new data which causing the collision will be lost. for receiving data, received data is transferred into a internal parallel read data buffer so that the shift register is free to accept a second byte. however, the received byte must be read from the data register( spdat ) before the next byte has been completely transferred. otherwise the previous byte is lost. wcol can be cleared in software by ?writing 1 to the bit?. http://www..net/ datasheet pdf - http://www..net/
stc12c5axx technical summary 61 typical timing diagram spi master transfer format with cpha=0 1 2345678 mosi (output) miso (input) driven from the target slave spclk/cpol=1 spclk/cpol=0 clock cycle target slave ss pin control gpio pin by software dord=0 dord=1 dord=0 dord=1 msb lsb 65 4 3 21 12 3 4 56 lsb msb 65 4 3 21 12 3 4 56 lsb msb msb lsb spen=1 and mstr=1, mosi turns to output data miso turns to input data spiclk is strongly output-driving. spen=0 or mstr=0, mosi switched not to output data of spi communication, also spiclk is released from spi control ss pin( if ssig=0) mov spdat,#data in software spi slave transfer format with cpha=1 1 2345678 miso (output) mosi (input) driven from master spclk/cpol=1 driven from master spclk/cpol=0 driven from master clock cycle ss pin (if ssig bit = 0 ) driven from master dord= 0 dord= 1 dord= 0 dord= 1 msb lsb 65 4 3 21 12 3 4 56 lsb msb 65 4 3 21 12 3 4 56 lsb msb msb lsb mosi turns to input miso turns to output spi slave transfer format with cpha=0 1 2345678 miso (output) mosi (input) driven from master spclk/cpol=1 driven from master spclk/cpol=0 driven from master clock cycle ss pin (if ssig bit = 0 ) driven from master dord= 0 dord= 1 dord= 0 dord= 1 msb lsb 65 4 3 21 12 3 4 56 lsb msb 65 4 3 21 12 3 4 56 lsb msb msb lsb mosi turns to input miso turns to output http://www..net/ datasheet pdf - http://www..net/
62 stc12c5axx technical summary spi master transfer format with cpha=1 1 2345678 mosi (output) miso (input) driven from the target slave spclk/cpol=1 spclk/cpol=0 clock cycle target slave ss pin control gpio pin by software dord=0 dord=1 dord=0 dord=1 msb lsb 65 4 3 21 12 3 4 56 lsb msb 65 4 3 21 12 3 4 56 lsb msb msb lsb spen=1 and mstr=1, mosi turns to output data miso turns to input data spiclk is strongly output- driving. spen=0 or mstr=0, mosi switched not to output data of spi communication, also spiclk is released from spi control ss pin( if ssig=0) mov spdat,#data in software http://www..net/ datasheet pdf - http://www..net/
stc12c5axx technical summary 63 analog to digital converter the adc on stc12c5axx an 10-bit resolution, successive-approximation approach, medium-speed a/d converter. v refp / v refm is the positive/negative reference voltage input for internal voltage-scaling dac use, the typical sink current on it is 600ua ~ 1ma. for stc12c5a, these two references are internally tied to vdd and gnd, separately. conversion is invoked since adc_start bit is set. prior to adc conversion, the desired i/o ports for analog inputs should be configured as input-only or open-drain mode first. the conversion takes around a fourth cycles to sample analog input data and other three fourths cycles in successive-approximation steps. total conversion time is controlled by two register bits ? speed1 and speed0 . analog input source comes from p1. x , one of the eight-channels is multiplexed by analog multiplexer into the comparator. when conversion is completed, the result will be saved onto { adc_res[7:0], adc_resl[1:0] } register. after the result has been loaded onto { adc_res[7:0], adc_resl[1:0] } register, adc_flag will be set. adc_flag associated with its enable register ie.5 ( eadc ). adc_flag should be cleared in software. the adc interrupt service routine vectors to 2b h . when the chip enters idle mode or power-down mode, the power of adc is turned off by hardware. p1.7(ain7) p1.6(ain6) p1.5(ain5) p1.4(ain4) p1.3(ain3) p1.2(ain2) p1.1(ain1) p1.0(ain0) + - 10-bit dac successive approximation regiter 10 chs2 chs1 chs0 speed1 spee d0 adc_ flag adc_ start adc_powe r comparator b9 b8 b7 b6 b5 b4 b3 b2 adc_res adc_contr b1 b0 ---- adc_resl -- vin ? v refm v refp - v refm {adc_res,adc_resl[1:0] = http://www..net/ datasheet pdf - http://www..net/
stc technology co.,ltd. stc12c5a08/16/32/60 8-bit micro-controller this document contains information on a new product under devel opment by stc.stc reserves the right to change or discontinue th is product without notice. 2007/12 version a1 sfr: adc_contr (adc control register) read/write address: 0xech default: 0xx0-0000 bit 7 6 5 4 3 2 1 0 name adc_power speed1 speed0 adc_fl ag adc_start chs2 chas1 chs0 adc_power := when clear shut down the pow er of adc block. when set turn on the power of adc block. {speed1, speed0} := conversion speed selector {0,0} := (default) a conversion takes 840 clock cycles {0,1} := a conversion takes 630 clock cycles {1,0} := a conversion takes 420 clock cycles {1,1} := a conversion takes 210 clock cycles adc_start := adc start control set to start an a/d conversion. it will be au tomatically cleared by the device after the device has finished the conversion. adc_flag := adc interrupt flag it will be set by the device after the devic e has finished a conversion, and should be cleared by the user?s software. {chs2, chs1, chs0} := input channel selector {0,0,0} := (default) set p1.0 as the a/d channel input {0,0,1} := set p1.1 as the a/d channel input {0,1,0} := set p1.2 as the a/d channel input {0,1,1} := set p1.3 as the a/d channel input {1,0,0} := set p1.4 as the a/d channel input {1,0,1} := set p1.5 as the a/d channel input {1,1,0} := set p1.6 as the a/d channel input {1,1,1} := set p1.7 as the a/d channel input http://www..net/ datasheet pdf - http://www..net/
stc12c5axx technical summary 65 sfr: adc_res ( adc value register ): read/write address: 0xbdh default: 0000-0000 bit 7 6 5 4 3 2 1 0 name the adc _ res is the final result from the a/d conversion. sfr: adc_resl (low byte of adc value register): read/write address: 0xbeh default: xxxx-xx00 bit 7 6 5 4 3 2 1 0 name the adc_resl (low bytes of adc value register ) http://www..net/ datasheet pdf - http://www..net/
66 stc12c5axx technical summary power management idle mode an instruction setting pcon .0 causes the device go into the idle mode, the internal clock is gated off to the cpu but not to the interrupt, timer, pca, spi, adc, wdt and serial port functions. there are two ways to termi nate the idle. activation of any enabled interrupt will cause pcon .0 to be cleared by hardware, terminating t he idle mode. the interrupt will be serviced, and following reti instruction, t he next instruction to be executed will be the one following the instruction that puts the device into idle. another way to wake-up from idle is to pull pin rst high to generate internal hardware reset. save power consumption under idle mode a clock divider(clkdiv) associated with idle mo de is used to slow down the system clock source in order to save power in advance. ev erybody knows that slower the clock oscillates, less power consumed. software could program this clock divider register prior to enter the idle mode. when the chip enters the idle mode, the cl ock is switched to the divider. when the chip exits the idle mode, clocking will re turn to the original clock behavior. sfr: clk_div ( power control ) read/write address: 0x97h default: xxxx-x000 bit 7 6 5 4 3 2 1 0 name cks2 cks1 cks0 {cks2, cks1, cks0}: clock selector under idle mode {0, 0,0} : = (default) in idle mode, clock is not divided (default state) {0, 0, 1} : = in idle mode, clock is divided by 2 {0, 1, 0} : = in idle mode, clock is divided by 4 {0, 1, 1} : = in idle mode, clock is divided by 8 {1, 0,0} : = in idle mode, clock is divided by 16 {1, 0, 1} : = in idle mode, clock is divided by 32 {1, 1, 0} : = in idle mode, clock is divided by 64 {1, 1, 1} : = in idle mode, clock is divided by 128 http://www..net/ datasheet pdf - http://www..net/
stc12c5axx technical summary 67 power-down mode an instruction setting pcon .1 causes the device go into the power-down mode. in the power-down mode, the on-chip oscillator is sto pped. the contents of on-chip ram and sfrs are maintained. the power-down mode can be woken-up by either pin rst event or interrupt from int0 or int1. when it is woken-up by rst, the prog ram will execute from the address 0x0000. be carefully to keep rst pin active for at least 10ms in order for a stable clock. if it is woken-up from pin int0 or int1, the cpu will rework throug h jumping to related interrupt service routine. before the cpu rework, the clock is blocked and counted until 32768 in order for de-bouncing the unstable clock. to use int0/int1 wake-up, interrupt-related regist ers have to be enabled and programmed accurately before entering power-down. pay attention to add at least one ?nop? instruction subsequent to the power-down instruction if i/o wake-up is used. sfr: pcon (power control) read/write address: 0x897h default: xxxx-x000 bit 7 6 5 4 3 2 1 0 name smod smod0 lvdf pof gf1 gf0 pd idl smod: = double baud rate of uart interface 0 : = keep normal baud rate when the uart is used in mode 1,2 or 3. 1 : = double baud rate when the uart is used in mode 1,2 or 3. smod0:= sm0 / fe bit select for sfr scon . 7 ; setting this bit will set sfr scon . 7 as frame error function. clearing it to set scon.7 as one bit of uart mode selection bits. (this bit is serial port related, see the further description about the serial port) lvdf: = low-voltage flag after power-up, this bit will be initially set. the user should clear it by his program. continuously on operating, it will be set if the power supply drops under 3.7v/2.3v (operate in the 5v/3v). pof: = power-on flag this bit will be set after the device was powered on. it must be cleared by the user?s software. pd: = power-down switch set this bit to drive the device enter power-down mode. http://www..net/ datasheet pdf - http://www..net/
68 stc12c5axx technical summary idl: = idle flag set this bit to drive the device enter idle mode. http://www..net/ datasheet pdf - http://www..net/
stc12c5axx technical summary 69 in system programming and in application programming in system programming (isp) to develop a good program for isp function, the user has to understand the architecture of the embedded flash. the embedded flash consists of 16 pages. each page contains 512 bytes. dealing with flash, the user must erase it in page unit before writing (programming) data into it. erasing flash means setting the content of that flash as ff h. two erase modes are available in this chip. one is mass mode and the other is page mode . the mass mode gets more performance, but it erases the entire flash. the page mode is something performance less, but it is flexible since it erases flash in page unit. unlike ram?s real-time operation, to erase flash or to write (program) flash often takes long time so to wait finish. furthermore, it is a quite complex timing proc edure to erase/program flash. fortunately, the stc12c5axx carried with convenient mechani sm to help the user read/change the flash content. just filling the target address and data into several sfr, and triggering the built-in isp automation, the user can easily er ase, read, and program the embedded flash. there are several sfr designed to help t he user implement the isp functionality. sfr: iap_data (isp flash data register) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 data to be written into fl ash, or data got from flash ifd is the data port register for isp/iap operation. the data in ifd will be written into the desired address in operating isp write and it is the data window of readout in operating isp read. sfr: iap_addrh (isp flash address high byte) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 must be cleared to 000 isp/iap address high byte ifadrh is the high byte address for all isp/iap operation. against in advertise effect, if one bit of ifadrh [7:5] is set, the isp write function must fail. sfr: iap_addrl (isp flash address low byte) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 isp/iap address low byte ifadrl is the low byte address for all isp/iap operation. sfr: iap_cmd (isp flash-operating mode table) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 - - - - - - mode selection http://www..net/ datasheet pdf - http://www..net/
70 stc12c5axx technical summary mode selection to operate 0 0 standby 0 1 ap-memory read 1 0 ap-memor y / data-flash program 1 1 ap-memor y / data-flash page erase sfr: iap_trig (isp sequential command register to trigger isp/iap operation) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 isp-command / device id sfr: iap_contr (iap control register) bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 iapen swbs swrst cfail - wait iapen: = determine if to enable isp/iap functionality 0 : = disable isp program to change flash. 1 : = enable isp program to change flash. swbs: = software boot entrance selector 0 : = boot from main-memory. 1 : = boot from isp memory. note: this bit will be loaded with hwbs(or0.3) after power-up moment. swrst: = software reset trigger setting this bit will ca use the device reset. cfail: = isp/iap command fail flag 0 : = the last isp/iap command ha s finished successfully. 1 : = the last isp/iap command fails. it could be caused since the access of flash memory was inhibited. wait: = waiting time selection while the flash is busy. cpu wait time (oscillato r cycle) iap_contr[2:0] page erase program read recommended system clock 0 0 0 672384 1760 2 30m~24m 0 0 1 504288 1320 2 24m~20m 0 1 0 420240 1100 2 20m~12m 0 1 1 252144 660 2 12m~6m 1 0 0 126072 330 2 6m~3m 1 0 1 63036 165 2 3m~2m 1 1 0 42024 110 2 2m~1m 1 1 1 21012 55 2 < 1m notice : software reset actions could reset other sfr, but it never influences bits iapen and swbs. the ispen and swbs only will be reset by power-up action, while not software reset. http://www..net/ datasheet pdf - http://www..net/
stc technology co.,ltd. stc12c5a08/16/32/60 8-bit micro-controller this document contains information on a new product under devel opment by stc.stc reserves the right to change or discontinue th is product without notice. 2007/12 version a1 procedures demonstrating isp function iap_cmd xxxxx 011 b /* choice page-erasing command */ iap_contr 100xx010 b /* set ispen=1 to enable flash change. set wait=010, 10942 mc; assumed 10m x?s*/ iap_addrh (page address high byte) /* specify the address of the page to be erased */ iap_addrl (page address low byte) iap_trig 5ah /* trig iap activity */ iap_trig a5h (cpu progressing will be hold here ) (cpu continues) erase a specific flash page iap_cmd xxxxx 010 b /* choice byte-programming command */ iap_contr 100xx010 b /* set ispen=1 to enable flash change. set wait=010, 60 mc; assumed 10m x?s*/ iap_addrh (address high byte) /* specify the address to be programmed */ iap_addrl (address low byte) iap_data (byte date to be written into flash) /* prepare data source */ iap_trig 5ah /* trig iap activity */ iap_trig a5h (cpu progressing will be hold here) (cpu continues) program a byte into flash iap_cmd xxxxx 001 b /* choice byte-read command */ iap_contr 100xx010 b /* set iapen=1 to enable flash change. set wait=010, 11 mc; assumed 10m x?s*/ iap_addrh (address high byte) /* specify the address to be read */ iap_addrl (address low byte) iap_trig 5ah /* trig isp activity */ iap_trig a5h (cpu progressing will be hold here) (cpu continues and currently iap_data contain the desired data byte ) read a byte from flash http://www..net/ datasheet pdf - http://www..net/
stc technology co.,ltd. stc12c5a08/16/32/60 8-bit micro-controller this document contains information on a new product under devel opment by stc.stc reserves the right to change or discontinue th is product without notice. 2007/12 version a1 in-application program (iap) the in-application program feature is designed for user to read/write nonvolatile data flash . it may bring great help to store parameters those should be independent of power-up and power-done action. in other word s, the user can store data in data flash memory, and after he shutting down the mcu and rebooting the mcu, he can get the original value, which he had stored in. the user can program the data flash according to the same way as isp program, so he should get deeper understanding related to sfr iap_data, iap_addrl, iap_addrh, iapcmd, iap_trig, and iap_contr . the data flash can be programmed by the ap program as well as the isp program. the isp program may program the ap memory and data flash , while the ap program may program the data flash but not the isp memory. if the ap program desires to change the isp memory associated with specific addre ss space, the hardware will ignore it. instructions set data trasfer mnemonic description byt cyc mov a, rn move register to acc 1 1 mov a, direct move direct byte o acc 2 2 mov a, @ri move indirect ram to acc 1 2 mov a, #data move immediate data to acc 2 2 mov rn, a move acc to register 1 2 mov rn, direct move direct byte to register 2 4 mov rn, #data move immediate data to register 2 2 mov direct, a move acc to direct byte 2 3 mov direct, rn move register to direct byte 2 3 mov direct, direct move direct byte to direct byte 3 4 mov direct, @ri move indirect ram to direct byte 2 4 mov direct, #data move immediate data to direct byte 3 3 mov @ri, a move acc to indirect ram 1 3 mov @ri, direct move direct byte to indirect ram 2 3 mov @ri, #data move immediate data to indirect ram 2 3 mov dptr,#data16 load dptr with a 16-bit constant 3 3 movc a,@a+dptr move code byte relative to dptr to acc 1 4 movc a,@a+pc move code byte relative to pc to acc 1 4 push direct push direct byte onto stack 2 4 pop direct pop direct byte from stack 2 3 xch a, rn exchange register with acc 1 3 xch a, direct exchange direct byte with acc 2 4 xch a, @ri exchange indirect ram with acc 1 4 xchd a, @ri exchange low-order digit indirect ram with acc 1 4 http://www..net/ datasheet pdf - http://www..net/
stc12c5axx technical summary 73 arithematic operations mnemonic description byt cyc add a, rn add register to acc 1 2 add a, direct add direct byte to acc 2 3 add a, @ri add indirect ram to acc 1 3 add a, #data add immediate data to acc 2 2 addc a, rn add register to acc with carry 1 2 addc a, direct add direct byte to acc with carry 2 3 addc a, @ri add indirect ram to acc with carry 1 3 addc a, #data add immediate data to acc with carry 2 2 subb a, rn subtract register from acc with borrow 1 2 subb a, direct subtract direct byte from acc with borrow 2 3 subb a, @ri subtract indirect ram from acc with borrow 1 3 subb a, #data subtract immediate data from acc with borrow 2 2 inc a increment acc 1 2 inc rn increment register 1 3 inc direct increment direct byte 2 4 inc @ri increment indirect ram 1 4 dec a decrement acc 1 2 dec rn decrement register 1 3 dec direct decrement direct byte 2 4 dec @ri decrement indirect ram 1 4 inc dptr increment dptr 1 1 mul ab multiply a and b 1 4 div ab divide a by b 1 5 da a decimal adjust acc 1 4 logic operation mnemonic description byt cyc anl a, rn and register to acc 1 2 anl a, direct and direct byte to acc 2 3 anl a, @ri and indirect ram to acc 1 3 anl a, #data and immediate data to acc 2 2 anl direct, a and acc to direct byte 2 4 anl direct, #data and immediate data to direct byte 3 4 orl a, rn or register to acc 1 2 orl a, direct or direct byte to acc 2 3 orl a, @ri or indirect ram to acc 1 3 orl a, #data or immediate data to acc 2 2 orl direct, a or acc to direct byte 2 4 orl direct, #data or immediate data to direct byte 3 4 xrl a, rn exclusive-or register to acc 1 2 xrl a, direct exclusive-or direct byte to acc 2 3 xrl a, @ri exclusive-or indirect ram to acc 1 3 xrl a, #data exclusive-or immediate data to acc 2 2 xrl direct, a exclusive-or acc to direct byte 2 4 xrl direct, #data exclusive-or immediate data to direct byte 3 4 clr a clear acc 1 1 cpl a complement acc 1 2 rl a rotate acc left 1 1 rlc a rotate acc left through the carry 1 1 rr a rotate acc right 1 1 rrc a rotate acc right through the carry 1 1 swap a swap nibbles within the acc 1 1 boolean variable manipulation mnemonic description byt cyc clr c clear carry 1 1 clr bit clear direct bit 2 4 setb c set carry 1 1 setb bit set direct bit 2 4 cpl c complement carry 1 1 cpl bit complement direct bit 2 4 anl c, bit and direct bit to carry 2 3 http://www..net/ datasheet pdf - http://www..net/
74 stc12c5axx technical summary anl c, /bit and complement of direct bit to carry 2 3 orl c, bit or direct bit to carry 2 3 orl c, /bit or complement of direct bit to carry 2 3 mov c, bit move direct bit to carry 2 3 mov bit, c move carry to direct bit 2 4 boolean variable branch mnemonic description byt cyc jc rel jump if carry is set 2 3 jnc rel jump if carry not set 2 3 jb bit, rel jump if direct bit is set 3 4 jnb bit, rel jump if direct bit not set 3 4 jbc bit, rel jump if direct bit is set and then clear bit 3 5 proagram braching mnemonic description byt cyc acall addr11 absolute subroutine call 2 6 lcall addr16 long subroutine call 3 6 ret return from subroutine 1 4 reti return from interrupt subroutine 1 4 ajmp addr11 absolute jump 2 3 ljmp addr16 long jump 3 4 sjmp rel short jump 2 3 jmp @a+dptr jump indirect relative to dptr 1 3 jz rel jump if acc is zero 2 3 jnz rel jump if acc not zero 2 3 cjne a, direct, rel compare direct byte to acc and jump if not equal 3 5 cjne a, #data, rel compare immediate data to acc and jump if not equal 3 4 cjne rn, #data, rel compare immediate data to register and jump if not equal 3 4 cjne @ri, #data, rel compare immediate data to indirect ram and jump if not 3 5 equal djnz rn, rel decrement register and jump if not equal 2 4 djnz direct, rel decrement direct byte and jump if not equal 3 5 nop no operation 1 1 ****** inhibited instruction ****** mnemonic description byt cyc movx a, @ri move external ram(8-bit address) to acc 1 3 movx a, @dptr move external ram(16-bit address) to acc 1 2 movx @ri, a move acc to external ram(8-bit address) 1 3 movx @dptr, a move acc to external ram(16-bit address) 1 2 http://www..net/ datasheet pdf - http://www..net/
stc12c5axx technical summary 75 absolute maximum rating (stc12c5axx) *1 tested by sampling dc characteristics (stc12c5axx) vss = 0v, ta = 25 , v cc = 5.0v unless otherwise specified symbol parameter test condition limits unit min typ max v ih1 input high voltage for p1 and p3 vcc=5.0v 2.0 v v ih2 input high voltage for reset pin vcc=5.0v 3.5 v v il input low voltage vcc=5.0v 0.8 v i ol output low current v pin =0.45v 12 20 ma i oh1 output high current(push-pull) v pin =2.4v 12 20 ma i oh2 output high current(quasi-bidirectional) v pin =2.4v 220 ua i il1 logic 0 input current(quasi-bidirectional) v pin =0.45v 17 50 ua i il2 logic 0 input current(input-only) v pin =0.45v 0 10 ua i lk input leakage current(open-drain output) v pin = v cc 0 10 ua i h2l logic 1 to 0 transition current v pin =1.8v 230 500 ua i op operating current f osc = 12mhz 12 30 ma i idle idle mode current f osc = 12mhz 6 15 ma i pd power down current v cc =5.0v 0.1 50 ua r rst internal reset pull-down resistance v cc =5.0v 100 kohm parameter rating operating voltage 4.5v ~ 5.5v operating temperature under bias -40 o c ~ 85 o c *1 storage temperature -40 o c ~ 125 o c voltage on any pin -0.5 ~ 5.5v operating frequency dc ~ 25mhz http://www..net/ datasheet pdf - http://www..net/
76 stc12c5axx technical summary absolute maximum rating (stc12le5axx) parameter rating operating voltage 2.4v ~ 3.6v operating temperature under bias -40 o c ~ 85 o c *1 storage temperature -40 o c ~ 125 o c voltage on any pin -0.5 ~ 3.6v operating frequency dc ~ 25mhz *1 tested by sampling dc characteristics (stc12le5axx) vss = 0v, ta = 25 , v cc = 3.3v unless otherwise specified symbol parameter test condition limits unit min typ max v ih1 input high voltage for p1 and p3 vcc=3.3v 2.0 v v ih2 input high voltage for reset pin vcc=3.3v 2.8 v v il input low voltage vcc=3.3v 0.8 v i ol output low current v pin =0.45v 8 14 ma i oh1 output high current(push-pull) v pin =2.4v 4 8 ma i oh2 output high current(quasi-bidirectional) v pin =2.4v 64 ua i il1 logic 0 input current(quasi-bidirectional) v pin =0.45v 7 50 ua i il2 logic 0 input current(input-only) v pin =0.45v 0 10 ua i lk input leakage current(open-drain output) v pin = v cc 0 10 ua i h2l logic 1 to 0 transition current(p1,3) v pin =1.4v 100 600 ua i op operating current f osc = 12mhz 9 15 ma i idle idle mode current f osc = 12mhz 3.5 6 ma i pd power down current v cc =3.3v 0.1 50 ua r rst internal reset pull-down resistance v cc =3.3v 100 kohm http://www..net/ datasheet pdf - http://www..net/
stc12c5axx technical summary 77 package dimension http://www..net/ datasheet pdf - http://www..net/
78 stc12c5axx technical summary version history version date page description a1 2008/09 initial issue - - - http://www..net/ datasheet pdf - http://www..net/

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